搜索资源列表
mb1504
- MB1504锁相环程序,已测试完毕-MB1504 PLL procedure has been tested. . . . . . . .
mb1504_430
- MB1504,430锁相环程序,已经调试通过-MB1504, 430 PLL procedure has been debugged. . . .
demoXEPKEY.mcp_0_backup
- FREESCALE 按键扫描程序。本程序主要包括以下功能: 1.设置锁相环和总线频率; 2.IO口使用; 3.SCI口使用:提供接收/发送字符、字符串、格式化字符串。 LED计数,根据灯亮可以读取系统循环了多少次-FREESCALE key scanner. This procedure includes the following features: 1. Setting PLL and the bus frequen
shu-si-fuo-xiang-huan
- 该压缩文件是一个用matlab实现数字锁相环仿真的程序-The compressed file is a digital PLL with matlab simulation program
DPLL
- 数字锁相环(DPLL)的介绍与硬件实现设计-Introduction and hardware design of Digital PLL (DPLL)
FLL
- 锁频环又称为自动频率控制(AFC)环,其利用反馈回路对输入频率变化进行调整,最后达到对频率的跟踪,广泛应用于雷达,卫星导航等领域对多普勒频率的跟踪。-Locked loop, also known as automatic frequency control (AFC) loop, the use of feedback loop to adjust the input frequency changes, and finally ac
pll0
- 搭建pll电路,主要包括鉴相器,低通滤波器,压控振荡器,包括个部分的输出信号-Pll circuit structures, including phase detector, low pass filter, VCO, including a part of the output signal
pll
- 基于simulink的频率合成器实现,可实现小数分频-Simulink-based frequency synthesizer implemented to achieve fractional
costas--m
- 本程序是用matlab程序语言编写的costas环仿真程序,并对于模拟的costas环的性能进行了分析,costas环主要用于载波同步,本设计实现了对于载波频率跟踪的实现,并且给出图形对比-The program is written in matlab program costas loop simulation program, and the simulated performance of costas loop analysi
pll_100M
- pll debug code,for quartus fpga,vhdl code for straxtix.
110519PLL
- 一个锁相环路,同相正交环路,一阶锁相环,做毕业设计时遇到的。-A phase-locked loop, quadrature-phase loop, the first order PLL, the design experience to do graduate.
pll
- verilog硬件描述语言实现数字锁相环功能仿真,-Digital phase-locked loop using verilog
PLL
- 主要的是介绍ARM外中断功能是如何设计和是使用的,共产考!-failed to translate
78P468
- EM78P468的4时钟C语音程序,利用TIMER1为中断记数,高频采用PLL方式-EM78P468 4 clock C voice procedure, and use TIMER1 interrupt count, high-frequency mode with PLL
rfm12_receive51
- RFM12是一款低成本的ISM频段FSK收发模块,其核心电路采用的是带锁相环(PLL)技术的RF12射频收发芯片. RFM12可工作在315/433/868/915MHz四个频段,并符合FCC和ETSI-RFM12 ISM band is a low-cost FSK transceiver modules, the core is used with a phase-locked loop circuit (PLL) technolo
DPLLdesign
- 数字锁相环频率合成器的设计,数字鉴相器,数字滤波器,数控振荡器,反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider
tuner
- How to build own FM receiver with PLL (SAA1057), remote control (RC5-code), digital controlled stereo audio processor (TDA7318), LCD (HD44780 compatible), all controlled by a PIC16F628.
me-lift-f
- MOTOROLA CPU me-lift-f经济型微机电梯控制系统用户手册主控制器采用性能优良稳定的美国MOTOROLA 公司的CPU,系统更可 靠。 MOTOROLA 的CPU 在工业控制领域占有重要地位,是世界上嵌入式处 理器最大的供货商,广泛应用于工业控制、汽车电子、消费电子的各个领域。 MOTOROLA CPU 内部集成看门狗电路,具有极强的抗干扰性能。 采用锁相环技术,能降低 CPU 外部频率,增强干扰
PLL_prj
- 对锁相环频率综合器进行仿真计算,以优化环路参数。-PLL frequency synthesizer for the simulation to optimize the loop parameters.
SG_FPGA
- 2006年电子设计竞赛二等奖,多功能函数、信号发生器核心器件FPGA内部的原理图,主要模块用VHDL代码描述,包括PLL、相位累加器、波形算法和正弦波查找表,可实现0.005Hz~20MHz的多波形信号产生,频率步进值0.005,输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generato