搜索资源列表
XUPV2P_User_Guide
- XUPV2P User Guide VirtexII Pro-XUPV2P VirtexII Pro User Guide
XUPV2P_User_Guide
- XUPV2P User Guide VirtexII Pro-XUPV2P VirtexII Pro User Guide
lab4
- Xilinx大学计划中EDK环境下的MB软核例程4源代码，版本为8.1，按照例程亲自编写，绝对可用！ -err
lab1
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验1简单的硬件设计实验-Xilinx-XUPV2P-based development platform for embedded system routine experiments: Experiment 1 a simple hardware design experiment
lab2
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验2为硬件设计添加IP-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: Experiment 2 for the hardware design to add IP
lab3
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验3为系统创建和添加自行定制IP-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: Experiment 3 for the system to create and add their own customized IP
lab4
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验4编写基本的应用程序-Xilinx-XUPV2P-based development platform for embedded system routine experiment: The experiment 4 was prepared in general applications
lab5
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验5高级应用程序编写-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: Experimental Advanced Application Programming 5
lab6
- 基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验6系统验证与调试-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: 6 experimental system to verify and debug
xupv2p-Hardware-Reference-Manul
- Xilinx的XUPV2P开发板硬件平台说明，包括固化例程测试的详细过程-Xilinx development board XUPV2P of hardware platforms, including test routines Curing the detailed process
ml310_base_linux_kernel_config
- xilinx FPGA，可用于xupv2p开发板的嵌入式Linux内核配置文件-Linux xupv2p
liushuideng
- 基于XILINX公司FPGA的流水灯代码，采用硬件描述语言VHDL-XILINX' s FPGA-based water lamp code, using hardware descr iption language VHDL
MP3-design-using-verilog
- 基于Xilinx XUPV2P平台(FPGA开发板)的MP3播放器设计-MP3 player design based on the the Xilinx XUPV2P platform (FPGA development board)
XUPV2P_User_Guide
- Xilinx XUPV2P User Guide
lab2
- 熟悉XUPV2P实验开发平台。熟悉掌握Verilog HDL语言并能用其建立基本 的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xi