搜索资源列表
5692-thphn72
- modding ddr 2 sd ram to 800mhz
黑金Sparten6开发板Verilog教程V1.6
- 黑金spartan的开发板教程，包含了各类接口如spi，uart，vga的用例，以及各项存储器如flash，ddr的操作方法(spartan 6 example design)
VmodCAM_Ref_HD Demo_13
- This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an
PS2
- Nexys 4 DDR上的鼠标接受测试程序(The mouse acceptance test program on Nexys 4 DDR)
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
JESD79-4
- JEDEC DDR4 spec 标准，是学习DDR的好资料(JEDEC DDR4 spec, good spec for understanding and studying DDR4)
main6678
- 6678工程应用，包含SRIO、net、PCIE、DDR3等接口，可以作为开发的参考文件(6678 engineering applications, including SRIO, net, PCIE, DDR3 and other interfaces, can be used as reference files for development.)
bemanitools-4.25
- bemanitools 4.25 for iidx/sdvx/ddr/pnm/etc
02Kintex*秘籍-MIG DDR应用3缓存设计
- vivado下的MIG教程,适用于XILINX 7系列FPGA(MIG tutorial under vivado.)
DDR4 JEDEC standard
- DDR4 SDRAM Specifications from JEDEC STANDARD. ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devi
海思3519A硬件设计指导
- 海思硬件电路设计资料，主要是3519A DDR设计
DDR2_SDRAM操作时序
- DDR2_SDRAM操作时序，介绍的很详细，不错(DDR2? SDRAM operation sequence, very detailed introduction, very good)
S02《Artix7*秘籍》MIG_DDR内存应用
- artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
konami bemanipc script
- konami bemanipc scr ipt for use of running ddr and gfdm
spicetools-latest-20201211
- Spice tools 2020 12 11 Can launch Bemani games, like IIDX, DDR, Reflec Beat, Nostalgia, JuBeat, etc. Also has built in e-amusement server which work for some (not all) games.(spicetools, 0 , spicetools\spicecfg.exe, 513
LVDS_to_eDP_Ncs8801s
- 1 Features Embedded-DisplayPort (eDP) Output 1/2/4lane eDP @ 1.62/2.7Gbps per lane UP to WQXGA (2560*1600) supported Up to 6dB pre-emphasis RGB Input 18/24bit RGB Interface Pixel clock up to 270MHz SDR/DDR suppor
海思芯片烧写工具与教程
- 海思Hi3751（64位4核A9架构CPU，主频1.5GHz ; 6核GPU，1G DDR、2K/4K H.265解码）是国内首款开发的智能电视主芯片，如图1所示。自此，国产智能彩电“无芯”状态成为历史。目前，海思Hi3751V620、Hi3751V510、Hi3751V551等芯片已成为TCL、长虹、创维、海信、康佳、海尔、夏普等多个品牌大屏幕4K智能电视的首选“心脏”，如康佳V600、创维G8200与H7、海信的K300和K700、