hogenauer cic滤波器的算法的研究及其与在fpga中的实现，简明易懂。

hogenauer cic滤波器的算法的研究及其与在fpga中的实现，简明易懂。-hogenauer cic filter algorithm and its relationship to the FPGA in the realization of easy to understand.

用verilog语言实现一个3级、抽取率为2的8位hogenauer CIC抽取滤波器-Verilog language to achieve a 3, the extraction rate of 8 hogenauer CIC decimation filter

hogen50(mm,n_bits) try hogen50(20,23) then hogen50(20,22) 4-stage Hogenauer filter for mm to 1 downsampling integer implementation simulating 2-compl arithmetic with n_bit accumulators- hogen50(mm,n_bits) try hog