搜索资源列表
clk_div3
- vhdl语言写的基数分频器，多平台，通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
ModelSimSEfangzhen
- modesim的时序仿真和功能仿真!从简单的开始,一步一步的教大家怎么用!
clk_div3
- vhdl语言写的基数分频器，多平台，通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
ModelSimSEfangzhen
- modesim的时序仿真和功能仿真!从简单的开始,一步一步的教大家怎么用!-modesim timing simulation and functional simulation! from simple to start, step by step and teach everyone how to use them!
200558080220
- 基于VHDL的自动售货机设计,希望对大家有点帮助-VHDL-based design of a vending machine, I hope all of you a little help
ModelSim_License
- Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定-Altera Modesim cracked
adder
- 高达16位加法器的实现，工作环境在ISE，modesim，该例程较为详细！-Up to 16-bit adder implementation, the working environment at ISE, modesim, the more detailed routines!
comparator
- 该程序能够实现多位数据的比较，运行环境为ISE，modesim，该程序代码简洁！-The program can achieve a number of data comparison, the operating environment for the ISE, modesim, the program code simple!
counter16
- 该程序为16位计数器，并带有缓存的功能，运行环境为ISE，modesim。-The program for 16-bit counters, with a cache of features, operating environment for the ISE, modesim.
iic
- 基于I2C总线协议，该程序用VHDL编写了该协议的源代码，运行环境为ISE，modesim-Based on the I2C bus protocol, the procedures used to prepare the protocol VHDL source code, runtime environment for the ISE, modesim
317
- modesim使用简介，包含PLD设计流程和相关内容。-About modesim use, including PLD design process and related content.
FIR_Direkt_BAB_P
- VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
modesim
- modsim软件的使用，是英文版本，对刚接触modsim的人很有帮助-modsim software use, is the English version, useful for people new to modsim
modelsim_pli_count
- 用count.v和count.c两个文件作为例子，用来说明modelsim的pLI使用方法-using two source files (count.v and count.c ) to demonstrate how to use modesim with PLI
DSP_FIR_Lab
- DSP的FIR实验，包含三种FIR实现形式，直接型，转置型，累加型，并且附带testbench,经过modesim测试没问题。-This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
modesim
- 讲述使用modelsim进行验证，使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档，对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog tes
eliminate_dithering
- 消抖电路的Verilog描述，经过modesim仿真，在板子上调试可行-Debounce Verilog descr iption of the circuit, after modesim simulation, debugging possible on the board
16qam
- simulink平台上实现16QAM的解调模型，并用XILINX ISE软件实现modesim仿真-Simulink on a platform of 16QAM demodulation models, modesim and XILINX ISE software simulation
Modelsim
- Modelsim百问第一章 modesim功能仿真遇到的问题-the problem about modesim
5B6B-codec
- verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal s