搜索资源列表
cmult
- 复乘法器的FPGA实现， 希望对初学者有帮助 -Complex Multiplier FPGA to achieve, and they hope to help beginners
multi16
- verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
mulf2m
- 椭圆曲线加密算法中的乘法器的生成，主要功能是实现在素域上的多项式模P(大素数）乘的运算。-Elliptic curve encryption algorithm to generate the multiplier, the main function is to achieve in the Su-domain polynomial module P (large prime numbers) by the operator.
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Wallace
- 一个关于Wallace树乘法器的论文，当中展示了一种改进后的wallace树乘法器方案，相比原来占用晶体管更少，效率更高-Wallace tree multiplier on the papers, which show an improved wallace tree multiplier after the program, compared to the original transistors occupy less effic
fir_parall
- 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the re
code
- code for booths multiplier
booth_multiplier
- Booth multiplier written in verilog
32bit
- multiplier and divider verilog codes
freqm
- frequency multiplier
FinalFPMultiplier
- Simple 32 bit Floating point Multiplier
Boothsmul
- Booths Multiplier using Behavioral Model
booth
- 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
DDS-baseddesignofthesinusoidalsignalgenerator
- 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
Multiplier
- 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
Multiplier
- 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
multiplier_8_bit
- This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder,