搜索资源列表
64SDRAM
- c64xx系列DSP的sdram测试程序-c64xx Series DSP sdram test procedures
DDR_SDRAM_use_in_embedded
- 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especial
DEC6713_SDRAM
- DSP的SDRAM调试的c源程序，开发板自带的，感兴趣的可-DSP SDRAM testing c source development to bring their own plates, be interested to s
bf533sdram
- ADI公司Blackfin系列DSP BF533读取SDRAM数据-ADI Blackfin BF533 Series DSP data read SDRAM
lattice_sdram_source_code
- lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
2006317163710945
- 本文主要解决在VXI总线模块上实现大容量动态存储器的技术难题，介绍了利用可编程逻辑器件实现数字信号处理器（DSP）与同步动态存储器（SDRAM）之间的数据读取逻辑的设计、编程思想，以及必要的硬件连接，编程方法等。-this paper to resolve the VXIbus module to achieve dynamic memory capacity of technical difficulties, introduced
sdram_5509
- 5509DSP对外部存储设备SDRAM进行设置并能成功进行访问-5509DSP right SDRAM external storage device can be set up and conducted successful visit
SDRAM_HY57V6416ET
- 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M** 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
core_2410
- 本文详细介绍了S3C2410CPU的引脚分布 还有内部SDRAM和NOR FLASH的连线情况-paper describes in detail the distribution of the pin S3C2410CPU there are internal SDRAM and NOR F LASH is the Connection
mt48lc4m32b2
- mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
SEEDVPM642_D1
- DM642开发板自带，包括音频，视频，SDRAM，UART等，此为其中之一。-DM642 development board to bring their own, including audio, video and SDRAM, UART, this is one of them.
SEEDVPM642_eeprom
- DM642开发板自带，包括音频，视频，SDRAM，UART等，此为其中之一。-DM642 development board to bring their own, including audio, video and SDRAM, UART, this is one of them.
DM642memory
- 测试DSP6400中SDRAM的程序。帮助大家了解DSP6400的存储器资源和调试CCS的过程.-SDRAM DSP6400 testing procedures. To help us all understand the DSP6400 memory resources and CCS debugging process.
FIFO_BEFORE
- 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
my_fifo_vhdl
- XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Init_SDRAM
- AT91RM9200 SDRAM初始化脚本文件，ADS1.2使用，SDRAM为三星K4S641632E，使用脚本后可以将代码直接通过JTAG下载到SDRAM中，在SDRAM中进行仿真调试，启动文件不要进行修改直接可以使用，同时打开CP15的指令缓存和数据缓存-AT91RM9200 SDRAM initialization scr ipt file, ADS1.2 use, Samsung K4S641632E of SDRAM, Aft
AN-SDRAM_SAM7SE_software_example
- 在用IAR开发AT91SAMSE系列中外扩sdram的源码。-IAR used in the development of a series of foreign expansion AT91SAMSE sdram the source.
SRAM_2
- FPGA的SDRAM控制器源程序 FPGA的SDRAM控制器源程序-FPGA SDRAM controller source FPGA SDRAM controller source
sdr_sdram
- 详细的SDRAM控制器HDL代码，最顶层代码，很清晰-detailed SDRAM controller HDL code top-level code, it was very clear