搜索资源列表
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
spi
- this the SPI slave module -this is the SPI slave module
i2c
- verilog语言实现i2c，在ise中调试仿真-verilog language i2c, debugging simulation in ise
fpga_ads8364
- fpga控制ti的多通道高精度ad芯片ads8364的verilog源码-fpga multi-channel high-precision control ti ad-chip ads8364 the verilog source code
FFT
- verilog 实现FFT IP核的控制，借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
DF2C8_13_DS18B20
- verilog实现单总线DS18B20温度测量-verilog DS18B20 temperature measurement single-bus
DS28E01-100-C-code-2008-4-29
- DS28E01 加密算法 C代码，经过测试没有问题。-DS28E01 C code
CRC16
- 用于CRC16校验的Verilog程序源代码，喜欢的拿走-Uses in CRC16 the verification the Verilog procedure source code, likes taking away
Verilog
- 比较详细的verilog课件和教程，包括清华的北大的 比较实用-More detailed verilog courseware and tutorials, including Tsinghua University Beijing University of more practical
MIT_Video-Scaler
- MIT的video scaler论文，文章后面附有c和verilog程序源代码，分为水平缩放和垂直缩放-MIT video scaler papers, articles, source code attached to the back, divided into horizontal scaling and vertical scaling
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别，从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive
VCO
- 压控振荡器的FPGA实现，Verilog语言完成。编译环境 ISE 13.2-The vco FPGA realizing, Verilog language completed. Compile environment ISE 13.2
hlh
- 绿灯、黄灯和红灯，交通灯实验veril源代码，与大家分享，在quartusII平台上实现。-Green, yellow and red lights, traffic lights experiment veril source code, to share with you, in quartusII platform.
Convolution
- 卷积程序的Verilog程序，实现卷积功能(Convolution program Verilog program to achieve convolution function)
FPGA设计秘笈
- FPGA新手必看，一些专业知识讲解的还是很仔细的。(FPGA novice must see, some professional knowledge is still very careful.)