搜索资源列表
Z-TURN-BOARD-V5-TOP
- zynq xilinx soc 7z020系列开发板的原理图文件，用户可参考此文件查看原理图。-Zynq xilinx soc 7 z020 series development board schematic diagram files, the user can refer to this file to check the schematic diagram.
project_zynq
- 使用ZYNQ创建一个控制外设的MicroBlaze-Use ZYNQ to create a control peripheral MicroBlaze
The_Zynq_Book
- 一本全面介绍ZYNQ的外文书籍，深入浅出，并结合实例讲述很精湛。-A comprehensive introduction to ZYNQ foreign language books, easy to understand, combined with examples of very skilled.
The_Zynq_Book_ebook_chinese
- 一本全面介绍ZYNQ的译本书籍，深入浅出，并结合实例讲述很精湛。-A comprehensive introduction to ZYNQ translation books, easy to understand, combined with examples of very skilled.
gpio_mio
- ZYNQ 的gpio 可以通过MIO 引出到PS 端的引脚，本例子 的gpio 通过MIO 引出，控制LED 灯D29。-ZYNQ GPIO can be drawn to the PS through the MIO pin, this example GPIO led by MIO, control LED lamp D29.
Tutorial---Unit-1
- Embedded System Design for Zynq unite-1
Lab3
- Use this code to practice zynq library
2015_2_zynq_labdocs_pdf
- These are bocks for Zynq FPGA
08_lwip
- zynq7000 下 lwip例程，经过测试，好用(zynq7000 lwip program)
u-boot-xlnx-xilinx-v2016.3.tar
- u-boot-xlnx-xilinx-v2016.3
Simple Open EtherCAT
- EtherCAT协议的开源实现，包括EtherCAT主站和从站(EtherCAT Master using SOEM Freescale i.MX53 Blackfin 5xx Blackfin 6xx Intel EtherCAT Slave using SOES Freescale K10 - using Beckhoff ET1100 Freescale K60 - u
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
Z-turn-examples-master
- # Z-turn-examples The repository with my simple Z-turn examples, to be used as templates for more serious projects. Please note, that the Buildroot configuration in my designs sets the root password to "test&quo
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products.
LAB2
- zynq上实现流水灯的软硬件协同设计，利用vivado 2015.2版本eda软件开发。(Zynq realizes the design of hardware and software of water lamp, and uses vivado version 2015.2 EDA software to develop it.)
ps_bram
- 通过ZYNQ的PS部分读写片上BRAM存储器(Read and write on-chip BRAM memory via the PS portion of the ZYNQ)
mem_wr
- 通过ZYNQ的PS部分读写DDR3存储器(Read and write the DDR3 memory via the PS portion of the ZYNQ)
zedboard_master_XDC_RevC_D_v3
- 在这个实验中，使用Mathworks HDL Coder工具产生一个LMS噪声消除的滤波器。HDL coder会基于Simulink模型生成RTL模型封装进IP核。这个滤波器可以自适应地将未知的噪声滤除，输出处理后的信号。(In this exeriment, the Mathworks HDL Coder tool is used to generate a LMS noise elimination filter. HDL code
S02_CH10_AXI_User_GPIO
- An example design of Zynq GPIO (zynq7010 board)
The_Zynq_Book_ebook_chinese
- The_Zynq_Book_ebook_chinese中文学习手册(The_Zynq_Book_ebook_chinese)