搜索资源列表
FPQ
- 分频器的vhdl描述,在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl descr iption of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
division
- 分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
time_div
- IP 分频器 可以通过输入参数而自动调整分频数-IP divider input parameters can be automatically adjusted at the frequency
zz
- 键控加/减计数器,将20MHz系统时钟经分频器后可得到5M、1M、100K、10K、5K、1K、10Hz、1Hz -Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
ab
- 能实现2分之1分频器,4分之1分频器,8分之1分频器等功能-To achieve half divider, prescaler fourth, eighth divider functions
ghzfchsa
- 数控分频器,可实现50m以内任意整数分频-NC divider can be realized within 50m of arbitrary integer frequency
quartus-work
- 基于FPGA的VERILOG的分频器的设计,10分频设计的源代码和设计思路-Based od FPGA
fenpinji
- 设计了一种分频器,能够将所给的频率分成较小的频率。可以适当修改其中的参数,使频率达到设计者要求-The design of a prescaler, which can be divided into smaller frequency to frequency. Appropriate changes to the parameters, so that the frequency of the designer to achieve
VHDL_100_1
- 第43例 四位移位寄存器 第44例 寄存/计数器 第45例 顺序过程调用 第46例 VHDL中generic缺省值的使用 第47例 无输入元件的模拟 第48例 测试激励向量的编写 第49例 delta延迟例释 第50例 惯性延迟分析 第51例 传输延迟驱动优先 第52例 多倍(次)分频器 第53例 三位计数器与测试平台 第54例 分秒计数显示器的行为描述6 第55例 地址计数器
int_div
- 基于fpga的任意频率的可计数分频器(奇偶数皆可)-frequency divide
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
cysteter
- 分频器,可以求出1--100000000Hz的所有的频率,基于xilinx公司的SPARTAN-3E板子。-Based on SPARTAN-3E of xilinx, using ISE and VHDL, i developed the cysteter.
verilog_divdier
- veilog中的常用分频器,包括2分频 4分频 8分频等 开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2
PFD50
- 分频器,利用D触发器做的2、3、5分频器-Divider, made use of D flip-flop divider 2,3,5
Freq_gen
- XILINX 分频器 100MHz,1KHz, 1Hz(XILINX frequency divider 100MHz, 1KHz, 1Hz)
plj
- 2秒闸门时间频率计,以及一个分频器,使用FPGA及verilog语言实现(2 second gate time frequency meter)
fenpin51
- 任意整数分频器,输出方波可调占空比(已仿真下板子验证)第一个系数为分频系数,第二个为高电平所占整个方波的比例(Arbitrary integer frequency divider, output square wave adjustable duty cycle (has been simulated under board verification), the first factor for the frequency divis
fenpin
- 用verilog语言设计了一个分频器,晶振频率为50MHz(A frequency divider is designed in Verilog language. The frequency of crystal oscillator is 50MHz)
oneMHZ
- VHDL语言编写的20Mhz分频器,时间为1秒(20Mhz frequency divider)
Divider
- 用Verilog HDL语言实现分频器,初学,简单(The realization of frequency divider in Verilog HDL, Elementary learning is simple)