资源列表
[VHDL编程] Carry_Select_Adder_Verilog
说明:进位选择加法器,verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.<张昊溢> 在 2025-09-22 上传 | 大小:3kb | 下载:0
[其他小程序] Model-Project.do
说明:Simulation Project created in ARENA for Production Management project.<mehmet> 在 2025-09-22 上传 | 大小:32kb | 下载:0
[VHDL编程] VeriRISC_CPU_Verilog
说明:Verilog硬件描述语言实现VeriRISC CPU。模块包含:8位寄存器,5位计数器,32*8 RAM,8位ALU,MUX,顺序控制器,时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo<张昊溢> 在 2025-09-22 上传 | 大小:9kb | 下载:0
[其他小程序] Ch3Solutions
说明:Simulation with Arena 4th Edition Chapter 03 Solutions<mehmet> 在 2025-09-22 上传 | 大小:125kb | 下载:0
[其他小程序] tpl_cleanlogic_2.3.0
说明:this template for joomla 22.5-this is template for joomla 22.5<venus53> 在 2025-09-22 上传 | 大小:715kb | 下载:0
[C#编程] SynoDemo_SynoAPI-for-WinCE
说明:比较难找的WINCE下的指纹仪开发示例代码,主要是针对压敏类指纹仪-More difficult to find the wince under the development of fingerprint device sample code, mainly for pressure-sensitive class fingerprint device<cnrenwy> 在 2025-09-22 上传 | 大小:3.88mb | 下载:0
[VHDL编程] bch_dec
说明:BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE<luobing> 在 2025-09-22 上传 | 大小:1.05mb | 下载:0
[微处理器(ARM/PowerPC等)] 2410_Exp1_GPIO
说明:系统基础实验之一:基于S3C2410在IAR5.3环境下调试通过嵌入式系统的GPIO程序。-One of the basic experiment of the system: Based on S3C2410 in IAR5.3 environment GPIO program debugging embedded systems.<张守祥> 在 2025-09-22 上传 | 大小:124kb | 下载:0
[微处理器(ARM/PowerPC等)] 2410_Exp2_Interrupt
说明:系统基础实验之二:基于S3C2410在IAR5.3环境下调试通过嵌入式系统的中断程序。-The basis of experimental system: based S3C2410 in the the IAR5.3 environment, debugging embedded systems through the interrupt routine.<张守祥> 在 2025-09-22 上传 | 大小:162kb | 下载:0