资源列表
[其他小程序] uart_rx
说明：Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL<hassan> 在 2025-10-14 上传 | 大小：1kb | 下载：0
[其他小程序] seven_seg_decoder
说明：ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment<hassan> 在 2025-10-14 上传 | 大小：1kb | 下载：0
[其他小程序] binary_to_bcd
说明：this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres<hassan> 在 2025-10-14 上传 | 大小：1kb | 下载：0
[Windows编程] CS22-1
说明：1602液晶字符显示实验從中會顯示不同的字 哪用起就會方便啦-1602 LCD character display experiments show different characters from which would be convenient to use since 啦<1602液晶字符显示> 在 2025-10-14 上传 | 大小：1kb | 下载：0