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[其他小程序] Example-3-1
说明:该程序是用quartus II作为开发工具,用verilog语言编写,实现全加器功能的实例。对初学者很有意义-The program is used as a quartus II development tools, using Verilog language, the realization of full-adder function example. Meaningful for beginners<xyq> 在 2025-06-11 上传 | 大小:1kb | 下载:0
[其他小程序] Example-4-1
说明:程序补充说明:对于时序逻辑,即always模块的敏感表为沿敏感信号(多为时钟或复位的正沿或负沿),统一使用非阻塞赋值“<=”-Procedures for additional information: For sequential logic, that is always sensitive table module along sensitive signals (clock or reset for a positive or negative along along), usin<xyq> 在 2025-06-11 上传 | 大小:17kb | 下载:0
[其他小程序] reg_counter
说明:程序补充说明:时钟输入:在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效,是由always敏感表中的posedge或negedge决定的 -Procedures for additional information: Clock Input: in each clock is along or negative along the data treatment. Clock is along the effective or negative along the effectiv<xyq> 在 2025-06-11 上传 | 大小:20kb | 下载:0
[其他小程序] buptxhxt2
说明:北京邮电大学信号与系统的课件,对于想考北京邮电大学硕士研究生的人挺有帮助的,乐于分享。-Beijing University of Posts and Telecommunications Signals and Systems courseware, the Beijing University of Posts and Telecommunications would like to test those who graduate quite helpful, happy to share.<左洪艳> 在 2025-06-11 上传 | 大小:19.11mb | 下载:0