资源列表
[其他小程序] uart_rx
说明：Tcode is in VERILOG HDL (Hardware descr iption language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL<hassan> 在 2025-11-23 上传 | 大小：1kb | 下载：0
[其他小程序] seven_seg_decoder
说明：ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment<hassan> 在 2025-11-23 上传 | 大小：1kb | 下载：0
[其他小程序] binary_to_bcd
说明：this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres<hassan> 在 2025-11-23 上传 | 大小：1kb | 下载：0
[其他小程序] RLECompress
说明：Windows program to compress the text<arshad> 在 2025-11-23 上传 | 大小：2kb | 下载：0
[其他小程序] frequencyresp_tutorial_vis
说明：控制系统PID例程，包含4个子VI，开闭环，分别用图形和m文件编程-PID control system routines, including the four sub-VI, open-loop, respectively, m file with the graphics and programming<Fred> 在 2025-11-23 上传 | 大小：525kb | 下载：0