资源列表
[软件工程] PluginExplorer-v11
说明:插件缓动工具,依然是greensock大神-greensock greensock greensock greensock<早点> 在 2025-10-01 上传 | 大小:320kb | 下载:0
[文件格式] HTML-world
说明:html标签快捷文档 html标签快捷文档-html worldhtml worldhtml worldhtml world<bbs> 在 2025-10-01 上传 | 大小:1.2mb | 下载:0
[软件工程] shuangshuru
说明:双计数器技术做除法在二项技术中方便使用,代码实验验证过-Double counter technique to do division<renchao> 在 2025-10-01 上传 | 大小:602kb | 下载:0
[行业发展研究] LowPowerTechniques
说明:Low Power Design Nano‐scale designs at 130nm and below are now confronted with a power dissipation level beyond the limits of IC packaging and cooling techniques • Consequently in many designs it is not possible to increase the clock speed<yosso> 在 2025-10-01 上传 | 大小:632kb | 下载:0
[行业发展研究] physicalDesign
说明:IL2200ASIC Design Physical Implementation Styles ASIC Design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification and Ener<yosso> 在 2025-10-01 上传 | 大小:1.57mb | 下载:0
[行业发展研究] RTL-coding-guidelines
说明:RTL coding guidelines Offer a collection of coding rules and guidelines. Make HDL Codes readable, modifiable, and reusable. Achieve optimal results in synthesis and simulation.<yosso> 在 2025-10-01 上传 | 大小:407kb | 下载:0
[行业发展研究] tutorial_asic_v12_1
说明:tutorial_asic_v12_1 Digital Design Flow Tutorial for EDA Tools: Synopsys Design Compiler Mentor Modelsim Cadence SOC Encounter<yosso> 在 2025-10-01 上传 | 大小:1.53mb | 下载:0
[行业发展研究] verilog_intro-Cygwin
说明:verilog_intro-Cygwin environment and as a design tool. The Cadence design tool suite is installed on the Linux servers on our network. We will use be using the GUI interface which will allow us to view waveforms in a timing diagram. This also r<yosso> 在 2025-10-01 上传 | 大小:552kb | 下载:0