资源列表
[软件工程] Verilog_HDL
说明:Verilog HDL程序设计教程,非常实用,对学习Verilog非常有用。<汪毅> 在 2025-07-06 上传 | 大小:10.35mb | 下载:0
[软件工程] Verilog_program
说明:Verilog语法手册,7件逻辑的实现与实验练习,非常实用,对学习Verilog编程很有帮助。-Verilog grammar manuals, 7 and experimental realization of the logic of practice, very practical, very helpful in learning Verilog programming.<汪毅> 在 2025-07-06 上传 | 大小:2.26mb | 下载:0
[软件工程] choosedevice
说明:文中给出了在数字系统设计时常用的器件,和它们的参数希望对大家有所帮助-The paper gives the design of digital systems in the commonly used devices, and their parameters would like to help everyone<qibinchuan> 在 2025-07-06 上传 | 大小:3.24mb | 下载:0
[技术管理] failure
说明:This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm<郑林> 在 2025-07-06 上传 | 大小:85kb | 下载:0
[技术管理] constraint
说明:This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm<郑林> 在 2025-07-06 上传 | 大小:167kb | 下载:0
[技术管理] budget
说明:This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm<郑林> 在 2025-07-06 上传 | 大小:167kb | 下载:0
[技术管理] unreliable
说明:This paper addresses a stochastic-#ow network in which each arc or node has several capacities and may fail. Given the demand d, we try to evaluate the system reliability that the maximum #ow of the network is not less than d. A simple algorithm<郑林> 在 2025-07-06 上传 | 大小:145kb | 下载:0
[行业发展研究] Improving
说明:Each arc of a binary-state network has good/bad states. The system reliability, the probability that source s communicates with sink t, can be computed in terms of minimal paths (MPs). An MP is an ordered sequence of arcs from s to t that has no<郑林> 在 2025-07-06 上传 | 大小:198kb | 下载:0
[软件工程] CPLDdesign
说明:文中给出了使用cpld设计数字系统的完全过程,希望对初学者有所帮助-In this paper, the use of CPLD design of the complete process of digital systems, and they hope to be helpful for beginners<> 在 2025-07-06 上传 | 大小:294kb | 下载:0
[软件工程] ClosedLoopPosition
说明:转角线位移式全闭环位置伺服系统及误差分析-Corner line displacement closed loop position servo system and error analysis<刘军> 在 2025-07-06 上传 | 大小:195kb | 下载:0