资源列表
[软件工程] Wildfire-stm32-board-schematics
说明：野火stm32开发板原理图,野火stm32开发板原理图-Wildfire stm32 board schematics,Wildfire stm32 board schematics<zhijun> 在 2025-05-21 上传 | 大小：100kb | 下载：0
[技术管理] SSD1963-Chinese-data
说明：SSD1963中文资料,SSD1963中文资料-SSD1963 Chinese data,SSD1963 Chinese data<zhijun> 在 2025-05-21 上传 | 大小：1.87mb | 下载：1
[软件工程] SSD1963-driver-Program
说明：SSD1963驱动程序，SSD1963驱动程序-SSD1963 driver Program，SSD1963 driver Program<zhijun> 在 2025-05-21 上传 | 大小：148kb | 下载：0
[编程文档] MIMOPredictionGlobecom2006Paper
说明：Research Paper for MIMO Wireless Channel<SNS> 在 2025-05-21 上传 | 大小：104kb | 下载：0
[成功激励] login
说明：Login test fall , no trojan, 54kb, code vip<lethienphu> 在 2025-05-21 上传 | 大小：4kb | 下载：0
[软件工程] verilog-a-lrm-1-0
说明：The information contained in this draft manual represents the definition of the Verilog-A hardware descr iption language as proposed by OVI (Analog TSC) as of January, 1996. Open Verilog International makes no warranti<bkaraca> 在 2025-05-21 上传 | 大小：211kb | 下载：0
[软件工程] verilog-ieee
说明：The Verilog ¤ Hardware Descr iption Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine re<bkaraca> 在 2025-05-21 上传 | 大小：2.08mb | 下载：0
[软件工程] SystemVerilog_3.1a
说明：Accellera Standards documents are developed within Accellera and the Technical Committees of Accellera Organization, Inc. Accellera develops its standards through a consensus development process, approved by its memb<bkaraca> 在 2025-05-21 上传 | 大小：2.82mb | 下载：0
[软件工程] VerilogLangRefManual
说明：The information contained in this draft manual represents the definition of the Verilog hardware descr iption language as it existed at the time Cadence Design Systems, Inc. transferred the language and its documentation<bkaraca> 在 2025-05-21 上传 | 大小：1.18mb | 下载：0