资源列表
[软件工程] adr_cntrl_timing
说明:对于得ddr2开发重要的文档,可以用fpga完成设计实现。-For the development of important documents have ddr2 can be used to complete the design fpga implementation.<ethan> 在 2025-06-11 上传 | 大小:7kb | 下载:0
[软件工程] Software-engineering-ideas
说明:软件工程基本观念,程序员与程序经理,项目计划与质量管理,可行性分析与需求分析,系统设计 ,C++ 面向对象程序设计,测试与改错,维护与再生工程-Basic concepts of software engineering, programmers and program managers, project planning and quality management, feasibility analysis and requirements analysis, system design,<taohai> 在 2025-06-11 上传 | 大小:1.4mb | 下载:0
[软件工程] simulink
说明:Binary Frequency Shift Keying (BFSK), the frequency of a constant amplitude carrier signal is switched between two values according to the two possible message states (called high and low tones) corresponding to a binary 1 or 0.Depending on how the f<miltung> 在 2025-06-11 上传 | 大小:111kb | 下载:0
[软件工程] t
说明:Binary Frequency Shift Keying (BFSK), the frequency of a constant amplitude carrier signal is switched between two values according to the two possible message states (called high and low tones) corresponding to a binary 1 or 0.Depending on how the f<miltung> 在 2025-06-11 上传 | 大小:2.16mb | 下载:0
[软件工程] silverlight-application-in-webgis
说明:silverlight在webgis中的应用-silverlight application in webgis<yuki> 在 2025-06-11 上传 | 大小:716kb | 下载:0
[软件工程] VTG-2600-system-program-book-rooms
说明:VTG-2600客房智能控制系统方案书 VTG-2600 intelligent control system program book rooms-VTG-2600 intelligent control system program book rooms<孙波> 在 2025-06-11 上传 | 大小:512kb | 下载:0
[软件工程] autorun
说明:Binary Frequency Shift Keying (BFSK), the frequency of a constant amplitude carrier signal is switched between two values according to the two possible message states (called high and low tones) corresponding to a binary 1 or 0.Depending on how the f<mailtung> 在 2025-06-11 上传 | 大小:1kb | 下载:0
[软件工程] Athan
说明:Binary Frequency Shift Keying (BFSK), the frequency of a constant amplitude carrier signal is switched between two values according to the two possible message states (called high and low tones) corresponding to a binary 1 or 0.Depending on how the f<afin> 在 2025-06-11 上传 | 大小:3.7mb | 下载:0
[软件工程] three-phase-phase-locked-loop-(-PLL-)
说明:three phase pll 5 harmunic<saeid> 在 2025-06-11 上传 | 大小:22kb | 下载:0
[软件工程] 1-Buck-DC-DC-Converter-Model
说明:buck dc dc converter model in matlab<saeid> 在 2025-06-11 上传 | 大小:17kb | 下载:0