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[软件工程] byljc
说明：本书共分5章。第1章介绍了博弈论的基本概念和几个典型的例子。第2章和第3章分别介绍了完全信息下的静态博弈和动态博弈；第4章和第5章则介绍了不完全信息下的静态博弈和动态博弈。-This book introduces one of the most powerful tools of modern economics to a wide audience: those who will later construct or consume game-theoretic models. Robert<王密码> 在 2025-07-03 上传 | 大小：18kb | 下载：0
[软件工程] Intro_to_VHDL
说明：Notes on VHDL (VHSIC Hardware Definition Language) A popular language for designing digital chips including FPGAs and CPLDs Notes on PERL, a popular scr ipting language-Notes on VHDL (VHSIC Hardware Definition Language) A popular language f<johnp> 在 2025-07-03 上传 | 大小：161kb | 下载：0
[软件工程] VHDL_Notes
说明：Notes ofn the VHDL. The VHDL (VHSIC Hardware Descr iptive language) is used for the design of ASIC, FPGA and CPLD integrated circuits-Notes ofn the VHDL. The VHDL (VHSIC Hardware Descr iptive language) is used for the design of ASIC, FPGA and CPLD i<johnp> 在 2025-07-03 上传 | 大小：793kb | 下载：0
[软件工程] verilog
说明：A popular cookbook describing the Verilog language for the design of integrated circuits. Verilog is the alternative to VHDL and is the favoured HDL design language in the USA. It is easier (quicker) to learn than VHDL because it is not so tightly ty<johnp> 在 2025-07-03 上传 | 大小：471kb | 下载：0
[软件工程] FSM-design
说明：An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog-An overview of Finite State Machines. FSMs are an important aspect of FPGA and CPLD desig using VHDL and Verilog<johnp> 在 2025-07-03 上传 | 大小：61kb | 下载：0
[软件工程] Java_Generics_And_Collections_2006
说明：In the past decade, Java has become the language of choice for a variety of applications. But Java developers have found themselves repeatedly referring to references such as Sedgewick s Algorithms in C for solutions to common programming problems. T<saurabh> 在 2025-07-03 上传 | 大小：904kb | 下载：0