文件名称:RAM_ROM_IP

  • 所属分类:
  • VHDL/FPGA/Verilog
  • 资源属性:
  • 上传时间:
  • 2020-08-02
  • 文件大小:
  • 600kb
  • 浏览/下载:
  • 1次 / 0次
  • 提 供 者:
  • CKQ1223
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明

RAM ROM ip核以及测试文件,方便新手学习ram和rom(RAM ROM ip core and test files)
相关搜索: verilog
FPGA

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
RAM_ROM_IP 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib\activehdl 0 2018-06-19
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib\ies 0 2018-06-19
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib\riviera 0 2018-06-19
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib\vcs 0 2018-06-19
RAM_ROM_IP\RAM_ROM_IP.cache\compile_simlib\xcelium 0 2018-06-19
RAM_ROM_IP\RAM_ROM_IP.cache\ip 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\914a00c44325469b.xci 6867 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\ROM_RAM_IP_dist_mem_gen_0_0.dcp 20446 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\ROM_RAM_IP_dist_mem_gen_0_0_sim_netlist.v 11406 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\ROM_RAM_IP_dist_mem_gen_0_0_sim_netlist.vhdl 19221 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\ROM_RAM_IP_dist_mem_gen_0_0_stub.v 1393 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b\ROM_RAM_IP_dist_mem_gen_0_0_stub.vhdl 1567 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b.logs 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\ip\2017.4\914a00c44325469b.logs\runme.log 28407 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\gui_handlers.wdf 7510 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\java_command_handlers.wdf 2112 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\project.wpc 61 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\synthesis.wdf 5424 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\webtalk_pa.xml 7017 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.cache\wt\xsim.wdf 256 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.hw 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.hw\RAM_ROM_IP.lpr 290 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\README.txt 130 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\ip 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\ip\RAM_ROM_IP_dist_mem_gen_0_0_1 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\ip\RAM_ROM_IP_dist_mem_gen_0_0_1\sim 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\ip\RAM_ROM_IP_dist_mem_gen_0_0_1\sim\RAM_ROM_IP_dist_mem_gen_0_0.v 3548 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\sim 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\RAM_ROM_IP\RAM_ROM_IP.srcs\sources_1\bd\RAM_ROM_IP\sim\RAM_ROM_IP.v 1213 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip\ROM_RAM_IP_dist_mem_gen_0_0 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip\ROM_RAM_IP_dist_mem_gen_0_0\ROM_RAM_IP_dist_mem_gen_0_0_sim_netlist.v 11430 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip\ROM_RAM_IP_dist_mem_gen_0_0\ROM_RAM_IP_dist_mem_gen_0_0_sim_netlist.vhdl 18933 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip\ROM_RAM_IP_dist_mem_gen_0_0\sim 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\ip\ROM_RAM_IP_dist_mem_gen_0_0\sim\ROM_RAM_IP_dist_mem_gen_0_0.v 3613 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\sim 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\bd\ROM_RAM_IP\sim\ROM_RAM_IP.v 1444 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\README.txt 3236 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\RAM_ROM_IP.sh 4870 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\RAM_ROM_IP.udo 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\README.txt 2186 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\compile.do 628 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\file_info.txt 467 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\glbl.v 1474 2017-12-14
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\simulate.do 326 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\activehdl\wave.do 32 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies\RAM_ROM_IP.sh 5669 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies\README.txt 2127 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies\file_info.txt 467 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies\glbl.v 1474 2017-12-14
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\ies\run.f 456 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\RAM_ROM_IP.sh 5124 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\RAM_ROM_IP.udo 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\README.txt 2186 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\compile.do 687 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\file_info.txt 467 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\glbl.v 1474 2017-12-14
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\simulate.do 330 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\modelsim\wave.do 32 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\RAM_ROM_IP.sh 5237 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\RAM_ROM_IP.udo 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\README.txt 2186 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\compile.do 663 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\elaborate.do 202 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\file_info.txt 467 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\glbl.v 1474 2017-12-14
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\simulate.do 197 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\questa\wave.do 32 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\RAM_ROM_IP.sh 4867 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\RAM_ROM_IP.udo 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\README.txt 2186 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\compile.do 618 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\file_info.txt 467 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\glbl.v 1474 2017-12-14
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\simulate.do 326 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\riviera\wave.do 32 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\vcs 0 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\vcs\RAM_ROM_IP.sh 6950 2018-06-15
RAM_ROM_IP\RAM_ROM_IP.ip_user_files\sim_scripts\RAM_ROM_IP\vcs\README.txt 2186 2018-06-15

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