文件名称:05_fifo_test

  • 所属分类:
  • VHDL/FPGA/Verilog
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  • 上传时间:
  • 2021-04-08
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  • 52.62mb
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  • 华仔1***
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介绍说明

FIFO: First in, First out 代表先进的数据先出,后进的数据后出。Xilinx 在 VIVADO 里为我们已经提供了 FIFO 的 IP 核, 我们只需通过 IP 核例化一个 FIFO,根据 FIFO 的读写时序来写入和读取FIFO 中存储的数据。(FIFO: first in, first out represents the first out of advanced data, and the last in data is the last out. Xilinx has provided us with the IP core of FIFO in vivado. We only need to instantiate a FIFO through the IP core, and write and read the data stored in FIFO according to the FIFO read-write timing.)
相关搜索: fpga;fifo;Verilog

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下载文件列表

文件名大小更新时间
05_fifo_test 0 2020-12-09
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