VHDL语言的UART串行接口芯片设计程序清单
附录1 数据接收据器的VHDL语言描述清单
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

ENTITY UART_receiver IS
PORT(RxD, Bclkx8, sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       setRDRF, setOE, setFE:OUT STD_lOGIC);
END UART_receiver;

ARCHITECTURE rtl OF UART_receiver IS

TYPE stateTYPE IS (R_WAiT, START_DETECTED,R_DATA);
SIGNAL state, nextstate:stateTYPE;
SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cnt1:INTEGER RANGE 0 TO 7;
SIGNAL cnt2:INTEGER RANGE 0 TO 8;
signal clr1,clr2 : std_logic;
SIGNAL inc1, inc2, shftRSR, loadRDR : STD_LOGIC;
SIGNAL Bclkx8_Dlayed, Bclkx8_rising:STD_LOGIC;

BEGIN
BclkX8_rising<=Bclkx8 AND (NOT Bclkx8_dlayed);
R_control:PROCESS(state,RxD,RDRF,cnt1,cnt2,BclkX8_rising)
BEGIN
--inc1<='0';inc2<='0';
--clr1<='0';clr2<='0';
shftRSR<='0'; loadRDR<='0'; setRDRF<='0'; setOE<='0'; 
setFE<='0';
CASE state IS
    WHEN R_WAIT =>
         IF(Rxd='0')THEN nextstate<=START_DETECTED;
            ELSE nextstate<=R_WAIT;
         END IF;
     WHEN START_DETECTED=>
            IF(Bclkx8_rising='0')THEN 
               nextstate<=START_DETECTED;
            ELSIF(RxD='1') THEN 
               clr1<='1';nextstate<=R_WAIT;
            ELSIF(cnt1=3) THEN 
               clr1 <='1'; nextstate<=R_WAIT;
            ELSE 
               inc1<='1';nextstate<=START_DETECTED; 
            END IF;
WHEN R_DATA =>
    IF(Bclkx8_rising='0') THEN nextstate<=R_DATA;
ELSE inc1<='1';
IF(cnt1 /= 7) THEN nextstate<=R_DATA;
ELSIF(cnt2/=8) THEN
      shftRSR<='1'; inc2<='1'; clr1<='1';
     nextstate<=R_DATA;
ELSE
     Nextstate<=R_WAIT;
     setRDRF<='1'; clr1<='1'; clr2<='1';
     IF(RDRF='1') THEN setOE<='1';
     ELSIF(RXD='0') THEN setFE<='1';
     ELSE loadRDR<='1';
     END IF;
                  END IF;
            END IF;
     END CASE;
END PROCESS;
R_update:PROCESS(sysclk,reset)
BEGIN
IF(reset='0') THEN state<=R_WAIT;BclkX8_Dlayed<='0';
     cnt1<=0; cnt2<=0;
ELSIF(syscLk'EVENT AND sysclk='1') THEN
    state<=nextstate;
    IF(clr1='1') THEN cnt1 <=0;
     ELSIF(inc1='1') THEN cnt1<=cnt1+1;
    END IF;
    IF(clr2='1') THEN cnt2<=0;
     ELSIF(inc2='1') THEN cnt2<=cnt2+1;
    END IF;
    IF(shftRSR='1') THEN RSR<= RxD & RsR(7 DOWNTO 1);
    END IF;
    IF(loadRDR='1') THEN RDR<=RSR;
   END IF;
   BclkX8_Dlayed<=BclkX8;
END IF;
END PROCESS;
END rtl;

附录2 数据发送器的VHDL语言描述清单
LIBRARY IEEE;
USE IEEE．STD_LOGIC_1164．ALL;

ENTITY UART_transmitter IS
PORT(
Bclk，sysclk，reset，TDRE，loadTDR：IN STD_LOGIC;
DBUS：INSTD_LOGIC_VECTOR(7 DOWNTO 0);
setTDRE，TxD：OUT STD_ LOGIC);
END UART_transmitter;

ARCHITECTURE rtl OF UART_transmitter IS
TYPEstateTYPE IS(T_WAlT，SYNCH，T—DATA);
SIGNAL state，nextstate：stateTYPE；
SIGNAL TDR：STD_LOGIC__VECTOR(7 DOWNTO 0)：
SIGNAL TSR：STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNALBcnt：INTEGER RANGE 0 TO 9;
SIGNAL inc，clr，loadTSR，shftTSR，start：STD-LOGIC;
SIGNAL Bclk_rising，Bclk_Dlayed：STD_LOGIC;
BEGIN
TxD<=TSR(0)：    
setTDRE<=loadTSR；
Bclk_rising<=Bclk AND (N0T Bclk_Dlayed);

T_control:PROCESS(state，TDRE，Bcnt，Bclk_rising)
BEGIN
inc=’0’：clr<='0'；loadTSR<=’0’；shftTSR<='0';
start<='0';    
CASE state IS
    WHEN T_WAIT=>
IF(TDRE=’0’)THEN loadTSR<=’1’nextstate<=SYNCH;
ELSE nextstate<=T_WAIT;
    END lF;
    WHEN SYNCH=>
IF(Bclk_rising=’1’)THEN start<=’1’;nextstate<=T_DATA;
    ELSE nextState<=SYNCH;
    END IF;
    WHENT_ DATA=>
    IF(Bclk_rising='0')THEN nextstate<=T_DATA;
    ELSIF(Bcnt／=9)THEN
       shftTSR='l';iucl;nextstate<=T_DATA;
    ELSE clr<=’1’;nextstate<=T_WAIT;
    END IF;
END CASE;
END PROCESS;

T_updale;PROCESS(sysclk,reset)
BEGIN
IF(reset=’0’)THEN
   TSR<=”111111111”;state<=T_WAIT,Bcnt<=0;Bclk_dlayed<=’0’;
ELSIF(sysclk’EVENT AND sysclk=’1’)THEN
    State<=nextstate;
IF(clr=’l’)THEN Bcnt<=0;ELSIF(inc=’l')THEN
                  Bcnt<=Bcnt+1;
END IF;
IF（loadTDR=T)THENTDR<=DBUS;ENDIF;
IF(loadTSR=‘1’)THEN TSR<=TDR&’1’;
ELSIF(START='I')THENTSR(0)<=‘0’;
ELSIF(shffrSR='1')THENTSR<='I，&TSR(8DOWNT01);ENDIF;
Bclk_Dlayed<=Bclk;
END IF; 
IF(loadTDR=’1’)THEN TDR<=DBUS;END IF;
IF(loadTSR=’1’)THER TSR<=TDR&’1’;
ELSEIF(START=’1’)THEN TSR(0),=’0’;
ELSEIF(shiftTSR=’1’)THEN TSR<=’1’&TSR(8 DOWNTO 1); 
END IF;
Bclk_Dlayed<=Bclk;

END IF;
END PROCESS;
END rtl;

附录3 波特率发生器的VHDL语言描述清单
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGlC_UNSIGNED.ALL;

ENTITY UART_clkdiv IS
POPT(
    sysclk:iN STD_LOGlC;
    sel:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
    BclkX8:BUFFER STD_LOGIC;
    Bclk:OUT STD_LOGIC);
END UART_clkdiv;

ARCHITECTURE rtl OF UART_clkdiv IS
SIGNAL divl:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL div2:STD_LOGIC_VECTOR (7 DOWNTO 0):="00000000";
SIGNAL div3:STD_LOGIC_VECTOR(2 DOWNTO 0)="000";
SIGNAL clkdivl3:STD_LOGIC;
BEGIN
div_13:prOCESS(syselk)
BEGIN
IF(sysclk'EVENT AND sysclk='1')THEN
    IF(div1="1100")THEN div1<="0000";
ELSE div1<=divl+1;
END IF;
END IF;
END PROCeSS;
BEGIN
IF(clkdivl3'VENT AND clkdivl3='1')THEN
    div2<=div2+l;
END IF;
END PROCESS;
clkdiv13<=div1(3);

div_pro:PROCESS(clkdiv13); 
BEGIN 
IF(clkdiv13'EVENT AND clkdiv13='1')THEN
   div2<=div2=1;
END IF; 
END PROCESS;
BclkX8<=div2(CONV_INTEGER(sel))；--select baud rate

div_8:pROCESS(BclkX8)
BEGIN
IF(BclkX8'EVENT AND BcLkXS='1')THEN
    div3<=dlv3+1;
    END IF;
    END PROCESS;
    bclk<=div3(2);
    END rtl;


附录4 UART总体的VHDL语言描述清单
LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.aLL;
    USE IEEe.STD_LOGIC_UNSIGNED.aLL;

ENTITY UART IS
PORT(
    reset, cs, R_W, clk, RxD, a1,a0:IN STD_LOGIC;
    d:INOUT STD_LOGiC_VECTOR(7 DOWNTO 0);
     IRQ, TxD:OUT STD_LOGIC);
END UART;

ARCHITECTURE rtl OF UART IS
COMPONENT UART_Receiver
     PORT(
      RxD,BclkX8,sysclk, reset, RDRF:IN STD_LOGIC;
       RDR:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    setRDRF, SETOE,setFE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_transmitter
PORT(
     Bclk,sysclk,reset, TDRE, IoadTDR:IN STD_LOGIC;
     DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     setTDRE, TxD:OUT STD_LOGIC);
END COMPONENT;
COMPONENT UART_clkdiv
PORT(
     Sysclk:IN STD_LOGIC;
     sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     BclkX8:BUFFER STD_LOGIC;
     Bclk:OUT STD_LOGIC);
END COMPONENT;
SIGNAL RDR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCSR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SCCR :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TDRE, RDRF, OE, FE, TIE, RIE:STD_LOGIC;
SIGNAL Baudsel :STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr :STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL setTDRE, setRDRF, setOE, setFE, loadTDR, loadSCCR:STD_LOGIC;
SIGNAL clrRDRF,Bclk,BclkX8,SCI_Read, SCI_Write:STD_LOGIC;
BEGIN
addr<=a1&a0;
u0:UART_Receiver PORT MAP(RxD,BclkX8,clk,reset,RDRF,RDR,setRDRF,setOE,setFE);
U1:UART_Transmitter PORT MAP(Bclk,clk,reset,TDRE,LoadTDR,d,
          setTDRE,TxD);                         
u2:UART_clkdiv PORT MAP(clk,Baudsel,BclkX8,Bclk);
PROCESS(clk, reset)
BEGIN
IF(reset='0') THEN
TDRE<='1'; RDRF<='0'; oE<='0'; FE<='0';
TIE<= '0'; RIE<='0';
ELSIF(clk'EVENT AND clk='1') THEN
TDRE<=(setRDRf AND NOT TDRE) OR (NOT loadTDR AND TDRE);
RDRF<=(setRDRF AND NOT RDRF) OR (NOT clrRDRF AND RDRF);
OE<=(setOE AND NOT OE) OR (NOT clrRDRF AND OE);
FE<=(setFE AND NOT FE) OR (NOT clrRDRF AND FE);
   IF(loadSCCR='1') THEN TIE<=d(7); RIE<=d(6);
                 Baudsel<=d(2 DOWNTO 0);
   END IF;
END IF;
END PROCESS;
IRQ<= '1' WHEN ((RIE='1' AND (RDRF='1' OR OE='1'))
                           OR(TIE='1'AND TDRE='1'))
ELSE
       '0';
SCSR<= TDRE & RDRF & "0000" & OE & FE;
SCCR<=TIE & RIE & "000" & Baudsel;
SCI_Read <='1' WHEN (cs='1'AND R_W='1') ELSE
                '0';
SCI_Write<= '1' WHEN (cs='1' AND R_W='0') ELSE
                 '0';
clrRDRF <='1' WHEN (SCI_Read='1' AND addr="00") ELSE
                '0';
loadTDR <='1' WHEN (SCI_Write='1' AND addr="00") ELSE 
                '0';
loadSCCR <='1' WHEN (SCI_Write='1' AND addr="10")ELSE
               '0';
d <="ZZZZZZZZ" WHEN (SCI_Read='0')ELSE
RDR        WHEN (addr="00")      ELSE
   SCSR        WHEN (addr="01")      ELSE
   SCCR;
END rtl;