搜索资源列表
状态机设计
- 详细说明状态机的设计，用VHDL实现，是不错的教程-detailed state machine design, VHDL, is a good guide
有限状态机设计与实现源代码
- 有限状态机设计与实现源代码.zip-finite state machine design and realization of the source code. Zip
7状态机设计
- 这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the scr ipt)", and I hope to learn VHDL is there to help the students, thank you!
有限状态机设计与实现源代码
- 有限状态机设计与实现源代码.zip-finite state machine design and realization of the source code. Zip
7状态机设计
- 这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the scr ipt)", and I hope to learn VHDL is there to help the students, thank you!
FSMGenerator10b7_win
- 状态机设计源代码-state machine design source code
uartok
- 采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
状态机设计
- 详细说明状态机的设计，用VHDL实现，是不错的教程-detailed state machine design, VHDL, is a good guide
uart_VHDL
- uart的vhdl实现代码 分模块设计和状态机设计 不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
112345
- 一篇经典状态机设计的资料，希望对大家有用-a classic state machine design information and useful for all
VHDL
- 基才VHDL状态机设计的智能交通控制灯 设计 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
VHDL
- 基才VHDL状态机设计的智能交通控制灯 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to see what
moore
- Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable sig
Mars
- 利用有限状态机设计的一个windows下的简易火星鼠游戏~通过此代码，可以研究一下状态机的机理-The use of finite state machine design windows under a simple mouse game Mars ~ through this code, you can look into the mechanism of state machine
mealy_state_machine
- 本程序为米勒状态机经典设计模块，对用状态机设计程序控制部分具有指导意义-This procedure for Miller classic state machine design modules, using state machine control part of the design of guiding significance for
UART
- UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧
esm
- 详细介绍了三种高效状态机设计，其中还有PDF格式的说明（英文版）。-Detailed information on the status of the three high-performance design, including descr iption of PDF format (in English).
sdh
- sdh帧处理过程，同步状态机设计，时钟分频设计，F1数据输出-sdh synchronization
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machin
verilog状态机
- 采用Verilog语言设计一个序列信号发生器和一个序列信号检测器，二者都以状态机模式实现。序列信号发生器输出8位宽度的序列信号“10110110”，通过数码管显示出来；序列信号发生器的输出接入序列信号检测器，检测器检测当前的输入信号，若出现目标序列信号则通过蜂鸣器输出一个声响，表示检测到有效的目标信号。(A sequence signal generator and a sequence signal detector are desi