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frequent
- 等精度频率计的设计，已经在实验箱上运行的。-such frequency accuracy of the design, the experiment has been running on the box.
ARM+FPGA
- 基于ARM平台的等精度数字显示频率计的设计,已通过测试-ARM-based platforms, such as the accuracy of figures show that the frequency of design, has been tested
Quartus_vhdl
- 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
freq
- 一个基于quartus2的等精度频率计的设计，主要采用的verilogＨＤＬ语言-Based on the quartus2 such as a precision frequency meter design, the main language used in verilogHDL
plj
- [frequent.rar] - 等精度频率计的设计，已经在实验箱上运行的。 -[frequent.rar]- such as the frequency accuracy of the design, the experiment has been running on me.
youname
- 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -Quartus compiler passed with precision frequency meter, etc., I am wrong, but there are several warning (excluding the impact of design). My graduation project ah! ! !
fre
- 基于等精度测频原理，设计的等精度频率计，测试结果很精确，达到0.01HZ。-Such as the accuracy of frequency measurement based on the principle of design, such as precision frequency meter, test results are accurate to 0.01HZ.
cpld11245
- 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-In
plj
- 等精度频率计的设计AT89C51，用单片机做的频率计，不错。-Such as the design of precision frequency meter AT89C51, to do with the frequency of single-chip, yes.
zhengwen
- 等精度频率计的毕业设计论文 是通过学校严格审查通过的Such as the accuracy of the frequency of graduate design thesis-Such as the accuracy of the frequency of graduate design thesis
frequentmeter
- 本设计是基于MCS-51单片机的等精度频率计。输入信号为峰峰值5v的正弦信号，频率测量范围10HZ~100MHZ ，频率测量精度为0.1 。采用1602液晶显示器显示测量结果。信号源由PROTEUS 的虚拟信号发生器产生。-The design is based on the MCS-51 microcontroller, such as frequency meter accuracy. Input signal 5v peak to
pinlvji
- 等精度频率计设计，很好的源代码，附上工程文件，在quartus5.0以上版本即可运行。-Design accuracy, such as frequency meter, a good source code, attached to the project document, in the above quartus5.0 to run.
E_8051_FTEST_K4X4_new
- 是带５１单片机核的等精度频率计的ＦＰＧＡ设计的部分。用ＶＨＤＬ编的，也有ＶＥＲＩＬＯＧ的。-51 is a single chip with precision, such as the nucleus of the frequency of some of FPGA design. VHDL for use as well as the VERILOG.
keshe
- 基于ａｔ８９ｓ５２设计的等精度频率计源程序-Based on the design at89s52 source such as precision frequency counter
zhengyu
- 基于FPGA技术的等精度频率计设计代码，已通过调试-Based on FPGA technology, such as precision frequency meter design code has been through the debugging
89C51pinlvjiLCD1602
- 本设计是基于MCS-51单片机的等精度频率计。输入信号为峰峰值5v的正弦信号，频率测量范围10HZ~100MHZ ，频率测量精度为0.1 。采用1602液晶显示器显示测量结果。信号源由PROTEUS 的虚拟信号发生器产生-This design is based on the MCS-51 microcontroller and other precision frequency meter. 5v peak to peak input
VHDL-djdplj
- 基于VHDL语言的十进制等精度频率计的设计，采用VHDL语言，运用自顶向下的设计思想， 将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。-VHDL language based on the decimal precision frequency meter, etc. The design, using VHDL language, the use of top-down design,
FPGA-VHDL-dengjingduc
- 本文介绍了基于VHDL语言的十进制等精度频率计的设计，采用VHDL 语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。 -This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use o
Frequency-counter
- 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL pr
基于FPGA的等精度频率计的设计
- 基于FPGA的频率计，采用的方法为等精度。(Frequency meter based on FPGA)