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msp430 Timer_A uart9600_06
- 利用MSP430的Timer A 模拟UART功能，波特率9600 32kHz ACLK-using MSP430 Timer A simulation function UART, 9600 Baud Rate 32kHz ACLK
fet440_wdt02
- MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, 32kHz ACLK-MSP-FET430P440 Demo - 14d Toggle P5.1 Inte rval overflow ISR, 32kHz ACLK
fet140_clks
- MSP-FET430P140 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK
MSP430adTransform
- 用比较器A进行斜边AD转换程序。 430F149:16位单片机平台,64K flash,2K RAM MCLK：8MHz ACLK：32.768kHz-A device used for comparison hypotenuse AD conversion. 430F149 : 16 MCU platform, 64K flash, 2K RAM MCLK : 8MHz ACLK : 32.768kHz
slac018e
- fet440_wdt_02.s43 - WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK
msp430x1xx_fet_1
- //*** *** *** *** *** *** *** // MSP430x1xx Demo - Software Toggle P1.0 // // Descr iption Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO // // MSP430x1xx
fet110_1
- //*** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1.0 // // Descr iption: Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO ~800k // // M
nand
- BCSCTL1 = 0X00 //将寄存器的内容清零 XT2震荡器开启 LFTX1工作在低ACLK的分频因子为1
msp430x11x1_ta_uart9600_04
- Descr iption: This program demonstrates a half-duplex 9600-baud UART using // Timer_A3 using no XTAL and an external resistor for DCO ROSC. DCO used for // TACLK UART baud generation. The program will wait in LPM4, e
fet120_clks
- MSP-FET430P120 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
fet410_ta
- MSP-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK Descr iption Toggle P5.1 using using software and TA_0 ISR. Toggle rate is set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TAC
d169_dma
- D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Descr iption A 32 byte block from 220h-240h is transfered to 240h-260h using DMA0 in a burst block using software DMAREQ trigger. After each transfer
fet140_spi
- MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Descr iption: Demonstrate USART0 in two-way SPI mode. Data are read from an HC165, and same data written back to the HC164. ACLK = n/a MCL
msp430x11x1_549
- 宣读了一份tlc549 ADC的参考vcc使用软件SPI和存储8位数字代码在adcdata 。该tlc549采样，在一个连续循环。如果adcdata > 0.5 * vcc ， p1.0设置，否则复位。aclk为N /甲mclk = smclk =预设会计处〜 800k vcc必须至少为3V为tlc549
fet440_uart11_38400
- Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK
msp430 Timer_A uart9600_06
- 利用MSP430的Timer A 模拟UART功能，波特率9600 32kHz ACLK-using MSP430 Timer A simulation function UART, 9600 Baud Rate 32kHz ACLK
fet440_wdt02
- MSP-FET430P440 Demo - WDT Toggle P5.1 Interval overflow ISR, 32kHz ACLK-MSP-FET430P440 Demo- 14d Toggle P5.1 Inte rval overflow ISR, 32kHz ACLK
fet140_clks
- MSP-FET430P140 Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK-MSP-FET430P140 Demo- Basic Clock, Output Buffered SMCLK, ACLK and MCLK
MSP430adTransform
- 用比较器A进行斜边AD转换程序。 430F149:16位单片机平台,64K flash,2K RAM MCLK：8MHz ACLK：32.768kHz-A device used for comparison hypotenuse AD conversion. 430F149 : 16 MCU platform, 64K flash, 2K RAM MCLK : 8MHz ACLK : 32.768kHz
slac018e
- fet440_wdt_02.s43 - WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK-fet440_wdt_02.s43- WDT, Toggle P5.1, Interval Overflow ISR, 32kHz ACLK