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DDS小数分频
- 文件列表(点击判断是否您需要的文件，如果是垃圾请在下面评价投诉): DDS小数分频 ...........\Block1.vhd.bak ...........\db ...........\..\add_sub_9mh.tdf ...........\..\DDS.asm.qmsg ...........\..\DDS.asm_labs.ddb ...........\..\DDS.cbx.
dds
- 直接数字频率合成器dds资料-Direct Digital Frequency Synthesizer dds information
dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and IS
DDS数字信号发生器
- DDS数字信号发生器,采用AD9835DDS 专用芯片 输出范围1K--10MHZ 采用X25045作看门狗及数据存储器，用于设置各项参数的存储 内含电路图， 源程序 及一些相关资料-DDS digital signal generator, using AD9835DDS ASIC output range 1K-- Knoxville watchdog for the use of X25045 and data memory, u
DDS+PLL
- 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
dds-design
- * DEscr iptION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DEscr iptION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Project1-DDS
- 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
dds-design
- DDS design with vhdl language.
AD9851-dds
- AD9851-dds的设计资料，原代码和原理图-AD9851- dds of design data, source code and the schematic diagram
DDS+51
- 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete
DDS
- 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation
DDS
- 详细介绍DDS的基本工作原理，并给出实际中常用的几款芯片的使用方法。-DDS detailed introduction of the basic working principle, and gives several commonly used in the actual use of the chip.
dds
- 用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
DDS
- dds->9954的pcb供大家参考,这个扳子我调通了的可以放心开办-dds-
FPGA--DDS-PhaseMeasure
- Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module c
3co---dds
- 直接数字频率合成（DDS）程序,使用adc9851芯片-Direct Digital Synthesis (DDS), the use of chip adc9851
dds
- 基于DDS的高性能信号源的设计 是pdf格式的哦-DDS-based high-performance signal source is designed to be Oh pdf format
DDS-2
- 用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
dds
- 此为基于ARM7编写的,采用周立功LPC2131系列ARM编写,用的是C语言,实现的是DDS AD9850 正弦波产生,晶振(参考频率)为PWM6产生,外围电路参照有关电路,不管何总都一样.-This is prepared based on the ARM7, the LPC2131 series ARM Ligong weeks to prepare, using the C language, realize that the D
DDS
- 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS