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Verilog_sourcecode
- 清华大学verilog hdl源码例子，作业，内含源代码，详细的文档说明，非常有用
VHDL 编程
- 包含源代码
Verilog_sourcecode
- 清华大学verilog hdl源码例子，作业，内含源代码，详细的文档说明，非常有用-Tsinghua University, verilog hdl code examples work, containing the source code, detailed documentation, very useful
4bit_buma_adder
- Verilog作业 ：自己写的源码输入，补码输出的，由状态机控制的四位加法器，为保证时序，加法器模块为超前近位加法器，包含测试台，通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four ad
verilog
- 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
MIPS
- 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, includ
veriloghomework
- 清华大学的verilog作业，里面有相应的例子和答案，作为练习相当的不错-Tsinghua University verilog operations, there are examples and the corresponding answers, as a very good practice
fir
- 做作业的时候用VERILOG编写的FIR滤波器程序，希望对大家有用-Homework time FIR filter with VERILOG written procedures, we want to be useful
exer4
- 设计可以对两个运动员赛跑计时的秒表，verilog的大作业 -Design of the two athletes running the stopwatch timing, verilog great job
project2_verilog
- 简化LAPS协议实现,verilog的大作业。-Simplify the LAPS protocol, verilog great job.
Computer-Architecture-lab1
- 计算机组成实验作业1，fpga开发板，verilog语言编写-Composition of experimental computer operating 1, fpga development board, verilog language
Computer-Architecture-lab2
- 计算机组成实验作业2，fpga开发板，verilog语言编写-Composition of experimental work computer 2, fpga development board, verilog language
Computer-Architecture-lab3
- 计算机组成实验作业3，fpga开发板，verilog语言编写-Composition of experimental computer operating 3, fpga development board, verilog language
Computer-Architecture-lab4
- 计算机组成实验作业4，fpga开发板，verilog语言编写-Composition of experimental computer operating 4, fpga development board, verilog language
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
verilog-hdl
- VHDL的各种算法算例，可供西电的大作业设计参考，是学习可编程语言的必备算例-VHDL examples of various algorithms available for Western Electric' s big job reference design is essential to learn a programming language examples
NEW
- Verilog投币式手机充电仪 清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger EDA major homework of digital electronic technology
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器，这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹，解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technolog
单周期CPU大作业-2020
- Verilog projects cpu
EDA-2
- 数字电子技术基础课程的第二次EDA作业，内容是投币充电仪。(The second EDA assignment of basic course of digital electronic technology is coin charger.)