搜索资源列表
pwm
- PWM Verilog HDL原码和底层C驱动，即测试程序，可直接使用
pwm发生器
- pwm发生器（原理图,pcb，程序流程图，源码80kc196）--PWM generator, including diagram, pcb, data flow diagram , and source code 80kc196).
PWMcontrolLED
- PWM占空比调节,控制小灯的渐明渐暗,程序简单明了-PWM duty cycle regulation, the control of small lights out gradually dimming, straightforward procedure
pwmled
- 一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak
pwm_VerilogHDLV1.1
- 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX ＰＬＵＳ ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
pwm
- 有关PWM的一些教程，适合初学者，需要的可以下载-PWM on the number of tutorials for beginners, what is needed can be downloaded
PWM
- 自己写的一个pwm模块，verilog的，是用于无刷电机控制的。-Himself wrote a pwm module, verilog is used for brushless motor control.
PWM
- Core_PWM,verilog语言编写，可用于电机驱动-Core_PWM, verilog language, can be used for motor drive
PWM
- Core_PWM,verilog语言编写，可用于电机驱动-Core_PWM, verilog language, can be used for motor drive
newlin-pwm
- VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制
cpld-pwm
- 基于cpld的pwm控制设计 采用vhdl.verilog语言设计 对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Source
- PWM Verilog源代码，可以通过仿真测试-PWM Verilog source code, can be tested through simulation
PWM
- 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
PWM
- verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
pwm
- verilog实现PWM 开发环境 QUARTUS II7.0-verilog to achieve PWM development environment QUARTUS II7.0
pwm
- pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
PWM-OUT
- 这里是一个比较好的用Verilog写的通过按键控制PWM输出从而控制小灯亮灭程度的经典例子~！~-Here is a better written in Verilog by using buttons to control the PWM output level of the control of small lights eliminate the classic example of ~! ~
pwm
- 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with t
PWM
- verilog描述 PWM IP核 内部包括载波 占空比 和时能寄存器-IP kernel of PWM based on Verilog hdl