verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transac