黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you