时钟模块作为soc设计中的关键模块，产生时钟和复位信号，要保证时钟无毛刺，复位能同步，保证整个系统工作的准确性- The accuracy of the clock module soc design as key modules, generates the clock and reset signals, the clock to ensure no glitches, reset can be synchronized to ensure that the entire system