VHDL设计中电路简化问题的探讨，从描述方法、设计规则、逻辑函数分析了VHDL设计中容易引起电路复杂化的原因，并提出了相应的解决方法。-VHDL design of simplified circuit explore, from the descr iption, design rules Logic function of VHDL design easily lead circuit complexity of the reasons, and the corresponding solu