在用VHDL语言设计中应充分利用VHDL语言特点,从设计思想语句运用及描述方法上等多方面对电路进行优化,举实例.-Using VHDL language design should make full use of VHDL language features, from design concept statement and descr iption of methods of use of first-class multi-circuit optimization, give examp