程序补充说明：对于时序逻辑，即always模块的敏感表为沿敏感信号（多为时钟或复位的正沿或负沿），统一使用非阻塞赋值“<=”-Procedures for additional information: For sequential logic, that is always sensitive table module along sensitive signals (clock or reset for a positive or negative along along), usin