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CAD algorithms for circuit layouts
- Source codes: src/cse788_layout.c - Code transform netlist output into magic file src/cse788_netlist.c - Implementation of optimzal netlist solver src/cse788_gordian.c - Implementation of gordian placement algorithm src/cse788_floorplan.c -
Technology Mapping : VLSI
- Input format: GraphML : graphml format contains nodes and edges of the graph. Output format: Testing: Done by VLSI TEAM
VLSI CAD ALGORITHMS
- Algorithms and data structures: efficient representation of graphs; Elementary graph algorithms involving bfs and dfs trees, such as finding connected and 2- connected components of a graph, the minimum spanning tree, shortest path between a pair of
A Maze Router
- An algorithm to route the wires in integrated circuits. The router handles 2 point nets, non-unit costs in the routing grid, bend penalties and uses 2 separate routing layers.
Domain Specific Hardware Accelerators: Vector Processing Units
- This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are impleme
FIR FILTER
- VLSI IMPLEMENTATION OF FIR FILTER
Comparative study of FFA architectures using different multiplier and adder topologies
- Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) give
A memory and area‑efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 D
- In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design