文件名称:Decoder_FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
这是Actel 的FPGA的译码器的VHDL源代码。-This is the Actel' s FPGA-Decoder VHDL source code.
相关搜索： actel
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Decoder_FPGA
............\component
............\.........\work
............\.........\....\decoder_top
............\.........\....\...........\decoder_top.cxf
............\.........\....\...........\decoder_top.sdb
............\.........\....\...........\decoder_top.v
............\constraint
............\coreconsole
............\Decoder.prj
............\designer
............\........\impl1
............\........\.....\ada00148-1.tmp
............\........\.....\decoder_top.adb
............\........\.....\decoder_top.dtf
............\........\.....\...............\verify.log
............\........\.....\decoder_top.ide_des
............\........\.....\decoder_top.pdb
............\........\.....\decoder_top.pdb.depends
............\........\.....\decoder_top.tcl
............\........\.....\decoder_top_fp
............\........\.....\..............\$$FlashPro_FPBBALTLPT1.L$$
............\........\.....\..............\decoder_top.log
............\........\.....\..............\decoder_top.pro
............\........\.....\..............\projectData
............\........\.....\..............\...........\decoder_top.pdb
............\........\.....\decoder_top_fp_1
............\........\.....\................\$$FlashPro_FPBBALTLPT1.L$$
............\........\.....\................\decoder_top.log
............\........\.....\................\decoder_top.pro
............\........\.....\................\projectData
............\........\.....\................\...........\decoder_top.pdb
............\........\.....\designer.log
............\........\.....\simulation
............\hdl
............\...\KEY.v
............\phy_synthesis
............\simulation
............\..........\modelsim.ini
............\..........\modelsim.ini.sav
............\smartgen
............\........\Decoder
............\........\.......\Decoder.cxf
............\........\.......\Decoder.gen
............\........\.......\Decoder.log
............\........\.......\Decoder.v
............\........\decoder_top_work.ixf
............\........\Decoder_work.ixf
............\........\KEY_work.ixf
............\........\smartgen.aws
............\stimulus
............\synthesis
............\.........\backup
............\.........\......\Decoder.srr
............\.........\......\decoder_top.srr
............\.........\coreip
............\.........\Decoder.areasrr
............\.........\Decoder.edn
............\.........\Decoder.map
............\.........\Decoder.sdf
............\.........\Decoder.so
............\.........\Decoder.srd
............\.........\Decoder.srm
............\.........\Decoder.srr
............\.........\Decoder.srs
............\.........\Decoder.tlg
............\.........\Decoder_sdc.sdc
............\.........\Decoder_syn.prj
............\.........\decoder_top.areasrr
............\.........\decoder_top.edn
............\.........\decoder_top.fse
............\.........\decoder_top.htm
............\.........\decoder_top.map
............\.........\decoder_top.sap
............\.........\decoder_top.sdf
............\.........\decoder_top.so
............\.........\decoder_top.srd
............\.........\decoder_top.srm
............\.........\decoder_top.srr
............\.........\decoder_top.srs
............\.........\decoder_top.tlg
............\.........\decoder_top_sdc.sdc
............\.........\decoder_top_syn.prj
............\.........\run_options.txt
............\.........\stdout.log
............\.........\syntmp
............\.........\......\Decoder.msg
............\.........\......\Decoder.plg
............\.........\......\decoder_top.msg
............\.........\......\decoder_top.plg
............\.........\......\decoder_top_flink.htm
............\.........\......\decoder_top_srr.htm
............\.........\......\decoder_top_toc.htm
............\.........\......\sap.log
............\viewdraw
............\........\sch
............\........\sym
............\........\vf
............\........\..\project.lst
............\........\viewdraw.ini
............\component
............\.........\work
............\.........\....\decoder_top
............\.........\....\...........\decoder_top.cxf
............\.........\....\...........\decoder_top.sdb
............\.........\....\...........\decoder_top.v
............\constraint
............\coreconsole
............\Decoder.prj
............\designer
............\........\impl1
............\........\.....\ada00148-1.tmp
............\........\.....\decoder_top.adb
............\........\.....\decoder_top.dtf
............\........\.....\...............\verify.log
............\........\.....\decoder_top.ide_des
............\........\.....\decoder_top.pdb
............\........\.....\decoder_top.pdb.depends
............\........\.....\decoder_top.tcl
............\........\.....\decoder_top_fp
............\........\.....\..............\$$FlashPro_FPBBALTLPT1.L$$
............\........\.....\..............\decoder_top.log
............\........\.....\..............\decoder_top.pro
............\........\.....\..............\projectData
............\........\.....\..............\...........\decoder_top.pdb
............\........\.....\decoder_top_fp_1
............\........\.....\................\$$FlashPro_FPBBALTLPT1.L$$
............\........\.....\................\decoder_top.log
............\........\.....\................\decoder_top.pro
............\........\.....\................\projectData
............\........\.....\................\...........\decoder_top.pdb
............\........\.....\designer.log
............\........\.....\simulation
............\hdl
............\...\KEY.v
............\phy_synthesis
............\simulation
............\..........\modelsim.ini
............\..........\modelsim.ini.sav
............\smartgen
............\........\Decoder
............\........\.......\Decoder.cxf
............\........\.......\Decoder.gen
............\........\.......\Decoder.log
............\........\.......\Decoder.v
............\........\decoder_top_work.ixf
............\........\Decoder_work.ixf
............\........\KEY_work.ixf
............\........\smartgen.aws
............\stimulus
............\synthesis
............\.........\backup
............\.........\......\Decoder.srr
............\.........\......\decoder_top.srr
............\.........\coreip
............\.........\Decoder.areasrr
............\.........\Decoder.edn
............\.........\Decoder.map
............\.........\Decoder.sdf
............\.........\Decoder.so
............\.........\Decoder.srd
............\.........\Decoder.srm
............\.........\Decoder.srr
............\.........\Decoder.srs
............\.........\Decoder.tlg
............\.........\Decoder_sdc.sdc
............\.........\Decoder_syn.prj
............\.........\decoder_top.areasrr
............\.........\decoder_top.edn
............\.........\decoder_top.fse
............\.........\decoder_top.htm
............\.........\decoder_top.map
............\.........\decoder_top.sap
............\.........\decoder_top.sdf
............\.........\decoder_top.so
............\.........\decoder_top.srd
............\.........\decoder_top.srm
............\.........\decoder_top.srr
............\.........\decoder_top.srs
............\.........\decoder_top.tlg
............\.........\decoder_top_sdc.sdc
............\.........\decoder_top_syn.prj
............\.........\run_options.txt
............\.........\stdout.log
............\.........\syntmp
............\.........\......\Decoder.msg
............\.........\......\Decoder.plg
............\.........\......\decoder_top.msg
............\.........\......\decoder_top.plg
............\.........\......\decoder_top_flink.htm
............\.........\......\decoder_top_srr.htm
............\.........\......\decoder_top_toc.htm
............\.........\......\sap.log
............\viewdraw
............\........\sch
............\........\sym
............\........\vf
............\........\..\project.lst
............\........\viewdraw.ini