文件名称:sdram
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 796kb
- 下载次数：
- 0次
- 提 供 者：
- l**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
一个RAM的测试仿真程序，有兴趣的朋友可以下载看看，希望对大家有所帮助-A RAM testing simulation program, interested friends can download and see, and they hope to help everyone
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ver15
.....\Bread_s.v
.....\Bread_s.v.bak
.....\Bwrite_s.v
.....\Bwrite_s.v.bak
.....\Command.v
.....\config_s.v
.....\control_interface.v
.....\main_s.v
.....\main_top.v
.....\modelsim.ini
.....\mod_ver15.cr.mti
.....\mod_ver15.mpf
.....\mt48lc8m16a2.v
.....\Params.v
.....\sdfsm_tb.v
.....\sdfsm_tb.v.bak
.....\sdr_data_path.v
.....\sdr_sdram.v
.....\transcript
.....\vsim.wlf
.....\work
.....\....\@bread_s
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\@bwrite_s
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\command
.....\....\.......\verilog.asm
.....\....\.......\_primary.dat
.....\....\.......\_primary.vhd
.....\....\config_s
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\control_interface
.....\....\.................\verilog.asm
.....\....\.................\_primary.dat
.....\....\.................\_primary.vhd
.....\....\main_s
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\main_top
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\mt48lc8m16a2
.....\....\............\verilog.asm
.....\....\............\_primary.dat
.....\....\............\_primary.vhd
.....\....\sdfsm_tb
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\sdr_data_path
.....\....\.............\verilog.asm
.....\....\.............\_primary.dat
.....\....\.............\_primary.vhd
.....\....\sdr_sdram
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\_info
.....\Bread_s.v
.....\Bread_s.v.bak
.....\Bwrite_s.v
.....\Bwrite_s.v.bak
.....\Command.v
.....\config_s.v
.....\control_interface.v
.....\main_s.v
.....\main_top.v
.....\modelsim.ini
.....\mod_ver15.cr.mti
.....\mod_ver15.mpf
.....\mt48lc8m16a2.v
.....\Params.v
.....\sdfsm_tb.v
.....\sdfsm_tb.v.bak
.....\sdr_data_path.v
.....\sdr_sdram.v
.....\transcript
.....\vsim.wlf
.....\work
.....\....\@bread_s
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\@bwrite_s
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\command
.....\....\.......\verilog.asm
.....\....\.......\_primary.dat
.....\....\.......\_primary.vhd
.....\....\config_s
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\control_interface
.....\....\.................\verilog.asm
.....\....\.................\_primary.dat
.....\....\.................\_primary.vhd
.....\....\main_s
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\main_top
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\mt48lc8m16a2
.....\....\............\verilog.asm
.....\....\............\_primary.dat
.....\....\............\_primary.vhd
.....\....\sdfsm_tb
.....\....\........\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\sdr_data_path
.....\....\.............\verilog.asm
.....\....\.............\_primary.dat
.....\....\.............\_primary.vhd
.....\....\sdr_sdram
.....\....\.........\verilog.asm
.....\....\.........\_primary.dat
.....\....\.........\_primary.vhd
.....\....\_info