文件名称:fpga_coder_module
介绍说明－－下载内容均来自于网络，请自行研究使用
本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.-FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.
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下载文件列表
压缩包 : 29782177fpga_coder_module.rar 列表 fpga编码器输入接口模块\F4.bdf fpga编码器输入接口模块\speed_code.TXT.bak fpga编码器输入接口模块\speed_code.TXT fpga编码器输入接口模块\Code_FD.bdf fpga编码器输入接口模块\LATCH1\LATCH1.qpf fpga编码器输入接口模块\LATCH1\LATCH1.qsf fpga编码器输入接口模块\LATCH1\LATCH1.map.eqn fpga编码器输入接口模块\LATCH1\LATCH1.map.rpt fpga编码器输入接口模块\LATCH1\LATCH1.flow.rpt fpga编码器输入接口模块\LATCH1\LATCH1.map.summary fpga编码器输入接口模块\LATCH1\LATCH1.fit.eqn fpga编码器输入接口模块\LATCH1\LATCH1.pin fpga编码器输入接口模块\LATCH1\LATCH1.fit.rpt fpga编码器输入接口模块\LATCH1\LATCH1.fit.summary fpga编码器输入接口模块\LATCH1\LATCH1.asm.rpt fpga编码器输入接口模块\LATCH1\LATCH1.tan.summary fpga编码器输入接口模块\LATCH1\LATCH1.tan.rpt fpga编码器输入接口模块\LATCH1\LATCH1.done fpga编码器输入接口模块\LATCH1\LATCH1.vwf fpga编码器输入接口模块\LATCH1\LATCH1.sim.rpt fpga编码器输入接口模块\LATCH1\LATCH1.qws fpga编码器输入接口模块\LATCH1\cmp_state.ini fpga编码器输入接口模块\LATCH1\LATCH1_assignment_defaults.qdf fpga编码器输入接口模块\LATCH1\LATCH1.sof fpga编码器输入接口模块\LATCH1\LATCH1.pof fpga编码器输入接口模块\LATCH1\LATCH1.bsf fpga编码器输入接口模块\LATCH1\Code_FD.bdf fpga编码器输入接口模块\LATCH1\LATCH1.v.bak fpga编码器输入接口模块\LATCH1\LATCH1.v fpga编码器输入接口模块\LATCH1\db\LATCH1.db_info fpga编码器输入接口模块\LATCH1\db\LATCH1.map.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.fit.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.sim.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.(0).cnf.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.hif fpga编码器输入接口模块\LATCH1\db\LATCH1.psp fpga编码器输入接口模块\LATCH1\db\LATCH1_cmp.qrpt fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.qrpt fpga编码器输入接口模块\LATCH1\db\LATCH1.cbx.xml fpga编码器输入接口模块\LATCH1\db\LATCH1.sim.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.rtlv_sg_swap.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.hier_info fpga编码器输入接口模块\LATCH1\db\LATCH1.(0).cnf.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sim.vwf fpga编码器输入接口模块\LATCH1\db\LATCH1.rtlv_sg.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.dbp fpga编码器输入接口模块\LATCH1\db\LATCH1.rtlv.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.map.logdb fpga编码器输入接口模块\LATCH1\db\LATCH1.pre_map.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sim.rdb fpga编码器输入接口模块\LATCH1\db\LATCH1.pre_map.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sgdiff.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.syn_hier_info fpga编码器输入接口模块\LATCH1\db\LATCH1.asm.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.tan.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.sgdiff.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.rpp.qmsg fpga编码器输入接口模块\LATCH1\db\LATCH1.sld_design_entry_dsc.sci fpga编码器输入接口模块\LATCH1\db\LATCH1.map.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.map.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sgate.rvd fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.logdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sgate_sm.rvd fpga编码器输入接口模块\LATCH1\db\LATCH1.eco.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.signalprobe.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.cdb fpga编码器输入接口模块\LATCH1\db\LATCH1_sim.qrpt fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp2.ddb fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.hdb fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.tdb fpga编码器输入接口模块\LATCH1\db\LATCH1.eds_overflow fpga编码器输入接口模块\LATCH1\db\LATCH1.asm_labs.ddb fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp.rdb fpga编码器输入接口模块\LATCH1\db\LATCH1.sim.qrpt fpga编码器输入接口模块\LATCH1\db\LATCH1.cmp0.ddb fpga编码器输入接口模块\LATCH1\db\LATCH1.sld_design_entry.sci fpga编码器输入接口模块\LATCH1\db fpga编码器输入接口模块\LATCH1\talkback\LATCH1.map.talkback.xml fpga编码器输入接口模块\LATCH1\talkback\LATCH1.fit.talkback.xml fpga编码器输入接口模块\LATCH1\talkback\LATCH1.asm.talkback.xml fpga编码器输入接口模块\LATCH1\talkback\LATCH1.tan.talkback.xml fpga编码器输入接口模块\LATCH1\talkback\LATCH1.sim.talkback.xml fpga编码器输入接口模块\LATCH1\talkback\LATCH1.rpp.talkback.xml fpga编码器输入接口模块\LATCH1\talkback fpga编码器输入接口模块\LATCH1 fpga编码器输入接口模块\F4\F4.qpf fpga编码器输入接口模块\F4\F4.qsf fpga编码器输入接口模块\F4\F4.qws fpga编码器输入接口模块\F4\cmp_state.ini fpga编码器输入接口模块\F4\F4.bdf fpga编码器输入接口模块\F4\F4.map.eqn fpga编码器输入接口模块\F4\F4.map.rpt fpga编码器输入接口模块\F4\F4.flow.rpt fpga编码器输入接口模块\F4\F4.map.summary fpga编码器输入接口模块\F4\F4.fit.eqn fpga编码器输入接口模块\F4\F4.pin fpga编码器输入接口模块\F4\F4.fit.rpt fpga编码器输入接口模块\F4\F4.fit.summary fpga编码器输入接口模块\F4\F4.asm.rpt fpga编码器输入接口模块\F4\F4.tan.summary fpga编码器输入接口模块\F4\F4.tan.rpt fpga编码器输入接口模块\F4\F4.done fpga编码器输入接口模块\F4\F4.vwf fpga编码器输入接口模块\F4\F4.sim.rpt fpga编码器输入接口模块\F4\F4_assignment_defaults.qdf fpga编码器输入接口模块\F4\F4.sof fpga编码器输入接口模块\F4\F4.pof fpga编码器输入接口模块\F4\F4.bsf fpga编码器输入接口模块\F4\F4.v fpga编码器输入接口模块\F4\db\F4.db_info fpga编码器输入接口模块\F4\db\F4.sim.qmsg fpga编码器输入接口模块\F4\db\F4.eco.cdb fpga编码器输入接口模块\F4\db\F4.map.qmsg fpga编码器输入接口模块\F4\db\F4.cmp.rdb fpga编码器输入接口模块\F4\db\F4.sld_design_entry.sci fpga编码器输入接口模块\F4\db\F4.cmp.qrpt fpga编码器输入接口模块\F4\db\F4.cbx.xml fpga编码器输入接口模块\F4\db\F4.hif fpga编码器输入接口模块\F4\db\F4.(0).cnf.cdb fpga编码器输入接口模块\F4\db\F4.(0).cnf.hdb fpga编码器输入接口模块\F4\db\F4.hier_info fpga编码器输入接口模块\F4\db\F4.pre_map.cdb fpga编码器输入接口模块\F4\db\F4.map.logdb fpga编码器输入接口模块\F4\db\F4.rtlv.hdb fpga编码器输入接口模块\F4\db\F4.rtlv_sg.cdb fpga编码器输入接口模块\F4\db\F4.rtlv_sg_swap.cdb fpga编码器输入接口模块\F4\db\F4.psp fpga编码器输入接口模块\F4\db\F4.dbp fpga编码器输入接口模块\F4\db\F4.sgdiff.cdb fpga编码器输入接口模块\F4\db\F4.syn_hier_info fpga编码器输入接口模块\F4\db\F4.sgdiff.hdb fpga编码器输入接口模块\F4\db\F4.fit.qmsg fpga编码器输入接口模块\F4\db\F4.pre_map.hdb fpga编码器输入接口模块\F4\db\F4.map.cdb fpga编码器输入接口模块\F4\db\F4_cmp.qrpt fpga编码器输入接口模块\F4\db\F4.cmp.logdb fpga编码器输入接口模块\F4\db\F4.map.hdb fpga编码器输入接口模块\F4\db\F4.sim.vwf fpga编码器输入接口模块\F4\db\F4.sim.rdb fpga编码器输入接口模块\F4\db\F4.eds_overflow fpga编码器输入接口模块\F4\db\F4.cmp0.ddb fpga编码器输入接口模块\F4\db\F4.cmp2.ddb fpga编码器输入接口模块\F4\db\F4.cmp.cdb fpga编码器输入接口模块\F4\db\F4.asm.qmsg fpga编码器输入接口模块\F4\db\F4.rpp.qmsg fpga编码器输入接口模块\F4\db\F4.tan.qmsg fpga编码器输入接口模块\F4\db\F4.sld_design_entry_dsc.sci fpga编码器输入接口模块\F4\db\F4.cmp.hdb fpga编码器输入接口模块\F4\db\F4.sim.hdb fpga编码器输入接口模块\F4\db\F4.cmp.tdb fpga编码器输入接口模块\F4\db\F4.sim.qrpt fpga编码器输入接口模块\F4\db\F4.asm_labs.ddb fpga编码器输入接口模块\F4\db\F4.sgate_sm.rvd fpga编码器输入接口模块\F4\db\F4.sgate.rvd fpga编码器输入接口模块\F4\db\F4.signalprobe.cdb fpga编码器输入接口模块\F4\db\F4_sim.qrpt fpga编码器输入接口模块\F4\db fpga编码器输入接口模块\F4\talkback\F4.sim.talkback.xml fpga编码器输入接口模块\F4\talkback\F4.rpp.talkback.xml fpga编码器输入接口模块\F4\talkback\F4.map.talkback.xml fpga编码器输入接口模块\F4\talkback\F4.fit.talkback.xml fpga编码器输入接口模块\F4\talkback\F4.asm.talkback.xml fpga编码器输入接口模块\F4\talkback\F4.tan.talkback.xml fpga编码器输入接口模块\F4\talkback fpga编码器输入接口模块\F4 fpga编码器输入接口模块\pusle_count\pulse_count.qpf fpga编码器输入接口模块\pusle_count\pulse_count.qsf fpga编码器输入接口模块\pusle_count\pulse_count.map.rpt fpga编码器输入接口模块\pusle_count\pulse_count.flow.rpt fpga编码器输入接口模块\pusle_count\pulse_count.map.summary fpga编码器输入接口模块\pusle_count\pulse_count.map.eqn fpga编码器输入接口模块\pusle_count\pulse_count.fit.eqn fpga编码器输入接口模块\pusle_count\pulse_count.pin fpga编码器输入接口模块\pusle_count\pulse_count.fit.rpt fpga编码器输入接口模块\pusle_count\pulse_count.fit.summary fpga编码器输入接口模块\pusle_count\pulse_count.asm.rpt fpga编码器输入接口模块\pusle_count\pulse_count.tan.summary fpga编码器输入接口模块\pusle_count\pulse_count.tan.rpt fpga编码器输入接口模块\pusle_count\pulse_count.done fpga编码器输入接口模块\pusle_count\pulse_count.vwf fpga编码器输入接口模块\pusle_count\pulse_count.sim.rpt fpga编码器输入接口模块\pusle_count\pulse_count.qws fpga编码器输入接口模块\pusle_count\cmp_state.ini fpga编码器输入接口模块\pusle_count\pulse_count_assignment_defaults.qdf fpga编码器输入接口模块\pusle_count\pulse_count.v.bak fpga编码器输入接口模块\pusle_count\pulse_count.v fpga编码器输入接口模块\pusle_count\pulse_count.sof fpga编码器输入接口模块\pusle_count\pulse_count.pof fpga编码器输入接口模块\pusle_count\pulse_count.bsf fpga编码器输入接口模块\pusle_count\db\pulse_count.db_info fpga编码器输入接口模块\pusle_count\db\pulse_count.sim.qmsg fpga编码器输入接口模块\pusle_count\db\pulse_count.sim.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.map.qmsg fpga编码器输入接口模块\pusle_count\db\pulse_count.fit.qmsg fpga编码器输入接口模块\pusle_count\db\pulse_count.rtlv_sg.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count_cmp.qrpt fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.logdb fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.qrpt fpga编码器输入接口模块\pusle_count\db\pulse_count.cbx.xml fpga编码器输入接口模块\pusle_count\db\pulse_count.hif fpga编码器输入接口模块\pusle_count\db\pulse_count.hier_info fpga编码器输入接口模块\pusle_count\db\pulse_count.(0).cnf.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.(0).cnf.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.pre_map.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.rtlv.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.map.logdb fpga编码器输入接口模块\pusle_count\db\pulse_count.psp fpga编码器输入接口模块\pusle_count\db\pulse_count.pre_map.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.sgdiff.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.dbp fpga编码器输入接口模块\pusle_count\db\pulse_count.sgdiff.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.map.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.map.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.syn_hier_info fpga编码器输入接口模块\pusle_count\db\pulse_count.sld_design_entry_dsc.sci fpga编码器输入接口模块\pusle_count\db\pulse_count.rtlv_sg_swap.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.asm.qmsg fpga编码器输入接口模块\pusle_count\db\pulse_count.tan.qmsg fpga编码器输入接口模块\pusle_count\db\pulse_count.sim.vwf fpga编码器输入接口模块\pusle_count\db\pulse_count.signalprobe.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.eco.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count_sim.qrpt fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.cdb fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp2.ddb fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.hdb fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.tdb fpga编码器输入接口模块\pusle_count\db\pulse_count.sim.rdb fpga编码器输入接口模块\pusle_count\db\pulse_count.asm_labs.ddb fpga编码器输入接口模块\pusle_count\db\pulse_count.eds_overflow fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp.rdb fpga编码器输入接口模块\pusle_count\db\pulse_count.sim.qrpt fpga编码器输入接口模块\pusle_count\db\pulse_count.cmp0.ddb fpga编码器输入接口模块\pusle_count\db\pulse_count.sld_design_entry.sci fpga编码器输入接口模块\pusle_count\db fpga编码器输入接口模块\pusle_count\talkback\pulse_count.map.talkback.xml fpga编码器输入接口模块\pusle_count\talkback\pulse_count.fit.talkback.xml fpga编码器输入接口模块\pusle_count\talkback\pulse_count.asm.talkback.xml fpga编码器输入接口模块\pusle_count\talkback\pulse_count.tan.talkback.xml fpga编码器输入接口模块\pusle_count\talkback\pulse_count.sim.talkback.xml fpga编码器输入接口模块\pusle_count\talkback fpga编码器输入接口模块\pusle_count fpga编码器输入接口模块\Code_FD\Code_FD.qpf fpga编码器输入接口模块\Code_FD\Code_FD.qsf fpga编码器输入接口模块\Code_FD\Code_FD.qws fpga编码器输入接口模块\Code_FD\F4.v fpga编码器输入接口模块\Code_FD\F4.bdf fpga编码器输入接口模块\Code_FD\Code_FD.map.rpt fpga编码器输入接口模块\Code_FD\Code_FD.flow.rpt fpga编码器输入接口模块\Code_FD\Code_FD.map.summary fpga编码器输入接口模块\Code_FD\Code_FD.bdf fpga编码器输入接口模块\Code_FD\LATCH1.bsf fpga编码器输入接口模块\Code_FD\F4.bsf fpga编码器输入接口模块\Code_FD\pulse_count.bsf fpga编码器输入接口模块\Code_FD\CodeFD.bdf fpga编码器输入接口模块\Code_FD\LATCH1.v fpga编码器输入接口模块\Code_FD\pulse_count.v fpga编码器输入接口模块\Code_FD\Code_FD.map.eqn fpga编码器输入接口模块\Code_FD\Code_FD.fit.eqn fpga编码器输入接口模块\Code_FD\Code_FD.pin fpga编码器输入接口模块\Code_FD\Code_FD.fit.rpt fpga编码器输入接口模块\Code_FD\Code_FD.fit.summary fpga编码器输入接口模块\Code_FD\Code_FD.sof fpga编码器输入接口模块\Code_FD\Code_FD.pof fpga编码器输入接口模块\Code_FD\Code_FD.asm.rpt fpga编码器输入接口模块\Code_FD\Code_FD.tan.rpt fpga编码器输入接口模块\Code_FD\Code_FD.done fpga编码器输入接口模块\Code_FD\Code_FD.v fpga编码器输入接口模块\Code_FD\Code_FD.vwf fpga编码器输入接口模块\Code_FD\Code_FD.sim.rpt fpga编码器输入接口模块\Code_FD\Code_FD.dpf fpga编码器输入接口模块\Code_FD\db\Code_FD.db_info fpga编码器输入接口模块\Code_FD\db\Code_FD.map.qmsg fpga编码器输入接口模块\Code_FD\db\Code_FD.rpp.qmsg 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fpga编码器输入接口模块\CFB_SP\CFB_SP.asm.rpt fpga编码器输入接口模块\CFB_SP\CFB_SP.tan.summary fpga编码器输入接口模块\CFB_SP\CFB_SP.tan.rpt fpga编码器输入接口模块\CFB_SP\CFB_SP.done fpga编码器输入接口模块\CFB_SP\CFB_SP.vwf fpga编码器输入接口模块\CFB_SP\CFB_SP.sim.rpt fpga编码器输入接口模块\CFB_SP\CFB_SP.qws fpga编码器输入接口模块\CFB_SP\LATCH1.v fpga编码器输入接口模块\CFB_SP\CFB_SP.v fpga编码器输入接口模块\CFB_SP\PULSE_COUNT.v fpga编码器输入接口模块\CFB_SP\db\CFB_SP.db_info fpga编码器输入接口模块\CFB_SP\db\CFB_SP.map.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.fit.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sim.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.tan.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.qrpt fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cbx.xml fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sim.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.logdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(0).cnf.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.pre_map.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sim.vwf fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sim.rdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(0).cnf.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.eds_overflow fpga编码器输入接口模块\CFB_SP\db\CFB_SP.rpp.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(2).cnf.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sim.qrpt fpga编码器输入接口模块\CFB_SP\db\CFB_SP.rtlv_sg_swap.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(2).cnf.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.map.logdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(3).cnf.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(3).cnf.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.map.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.rtlv_sg.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.rtlv.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.hif fpga编码器输入接口模块\CFB_SP\db\CFB_SP.pre_map.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sgdiff.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.asm.qmsg fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sgdiff.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sld_design_entry_dsc.sci fpga编码器输入接口模块\CFB_SP\db\CFB_SP.map.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.eco.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(1).cnf.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.(1).cnf.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sgate.rvd fpga编码器输入接口模块\CFB_SP\db\CFB_SP.signalprobe.cdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.hier_info fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp2.ddb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.hdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.tdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.asm_labs.ddb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp.rdb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sgate_sm.rvd fpga编码器输入接口模块\CFB_SP\db\CFB_SP.cmp0.ddb fpga编码器输入接口模块\CFB_SP\db\CFB_SP.sld_design_entry.sci fpga编码器输入接口模块\CFB_SP\db\CFB_SP.psp fpga编码器输入接口模块\CFB_SP\db\CFB_SP.dbp fpga编码器输入接口模块\CFB_SP\db\CFB_SP.syn_hier_info fpga编码器输入接口模块\CFB_SP\db fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.sim.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.rpp.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.map.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.fit.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.asm.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback\CFB_SP.tan.talkback.xml fpga编码器输入接口模块\CFB_SP\talkback fpga编码器输入接口模块\CFB_SP fpga编码器输入接口模块