文件名称:7[1].7
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异步数据传输vhdl实现，需要具体设计要求的人能可以联系我。-asynchronous data transmission vhdl reality requires specific design requirements of the people can contact me.
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压缩包 : 416950297[1].7.rar 列表 M1\project\project.dhp M1\project\toppart.ngr M1\project\toppart.ngc M1\project\project.ise M1\project\toppart.bld M1\project\project.ise_ISE_Backup M1\project\__projnav\sumrpt_tcl.rsp M1\project\__projnav\runXst_tcl.rsp M1\project\__projnav\project_flowplus.gfl M1\project\__projnav\project.gfl M1\project\__projnav\toppart.xst M1\project\__projnav\ednTOngd_tcl.rsp M1\project\__projnav\nc1TOncd_tcl.rsp M1\project\__projnav\parFloorPlanner.rsp M1\project\__projnav\parentCreateTimingConstraintsApp_tcl.rsp M1\project\__projnav\pfea_tcl.rsp M1\project\__projnav\parentAssignPackagePinsApp_tcl.rsp M1\project\__projnav.log M1\project\automake.log M1\project\toppart.prj M1\project\toppart.lso M1\project\toppart.cmd_log M1\project\toppart.syr M1\project\toppart.ngd M1\project\toppart.nc1 M1\project\toppart.stx M1\project\xst\work\sub00\vhpl00.vho M1\project\xst\work\sub00\vhpl01.vho M1\project\xst\work\sub00\vhpl02.vho M1\project\xst\work\sub00\vhpl03.vho M1\project\xst\work\sub00\vhpl04.vho M1\project\xst\work\sub00\vhpl05.vho M1\project\xst\work\sub00\vhpl06.vho M1\project\xst\work\sub00\vhpl07.vho M1\project\xst\work\hdllib.ref M1\project\xst\work\hdpdeps.ref M1\project\toppart_summary.html M1\project\_ngo\dpram16b16w.ngo M1\project\_ngo\netlist.lst M1\project\toppart.par M1\project\toppart.ncd M1\project\.untf M1\project\toppart.xpi M1\project\toppart.pad M1\project\toppart.twx M1\project\toppart_map.ngm M1\project\toppart.pcf M1\project\toppart_map.ncd M1\project\toppart.mrp M1\project\toppart.ngm M1\project\toppart_pad.csv M1\project\toppart_pad.txt M1\project\__ISE_repository_project.ise_.lock M1\project\toppart.placed_ncd_tracker M1\project\toppart.twr M1\project\toppart.pad_txt M1\project\toppart.cel M1\project\toppart.fnf M1\project\toppart.ucf M1\project\toppart.ucf.untf M1\project\toppart_last_par.ncd M1\project\toppart.routed_ncd_tracker M1\project\toppart_fpga_editor.log M1\macro\dpram16b16w_readme.txt M1\macro\dpram16b16w.asy M1\macro\dpram16b16w.edn M1\macro\dpram16b16w.sym M1\macro\dpram16b16w.v M1\macro\dpram16b16w.veo M1\macro\dpram16b16w.vhd M1\macro\dpram16b16w.vho M1\macro\dpram16b16w.xco M1\macro\dpram16b16w_flist.txt M1\ucf\toppart.ucf RTL\toppart.vhd RTL\clkpart.VHD RTL\readpart.VHD RTL\writepart.vhd SIM\tb_00.do SIM\vsim.wlf SIM\tb_01.do SIM\tb_02.do SIM\tb_09.do SIM\tb_03.do SIM\tb_04.do SIM\tb_05.do SIM\tb_06.do SIM\tb_07.do SIM\tb_08.do SIM\wave_09.do SIM\work\_info SIM\work\tb_09\_primary.dat SIM\work\tb_09\_vhdl.asm SIM\work\tb_08\_primary.dat SIM\work\tb_08\_vhdl.asm SIM\work\tb_07\_primary.dat SIM\work\tb_07\_vhdl.asm SIM\work\tb_06\_primary.dat SIM\work\tb_06\_vhdl.asm SIM\work\tb_05\_primary.dat SIM\work\tb_05\_vhdl.asm SIM\work\tb_04\_primary.dat SIM\work\tb_04\_vhdl.asm SIM\work\tb_03\_primary.dat SIM\work\tb_03\_vhdl.asm SIM\work\tb_02\_primary.dat SIM\work\tb_02\_vhdl.asm SIM\work\tb_01\_primary.dat SIM\work\tb_01\_vhdl.asm SIM\work\tb_00\_primary.dat SIM\work\tb_00\_vhdl.asm SIM\work\tb_vec\_primary.dat SIM\work\tb_vec\behavior.dat SIM\work\tb_vec\behavior.asm SIM\work\tbclk40_vec\_primary.dat SIM\work\tbclk40_vec\behavior.dat SIM\work\tbclk40_vec\behavior.asm SIM\work\tbclk66_vec\_primary.dat SIM\work\tbclk66_vec\behavior.dat SIM\work\tbclk66_vec\behavior.asm SIM\work\tb\_primary.dat SIM\work\tb\behavior.dat SIM\work\tb\behavior.asm SIM\work\dpram16b16w\_primary.dat SIM\work\dpram16b16w\dpram16b16w_a.dat SIM\work\dpram16b16w\dpram16b16w_a.asm SIM\work\clkpart\_primary.dat SIM\work\clkpart\archclk.dat SIM\work\clkpart\archclk.asm SIM\work\readpart\_primary.dat SIM\work\readpart\archread.dat SIM\work\readpart\archread.asm SIM\work\writepart\_primary.dat SIM\work\writepart\archwrite.dat SIM\work\writepart\archwrite.asm SIM\work\toppart\_primary.dat SIM\work\toppart\archtop.dat SIM\work\toppart\archtop.asm SIM\tb_ptn\tb_01\din.txt SIM\tb_ptn\tb_01\dout.txt SIM\tb_ptn\tb_01\err.txt SIM\tb_ptn\tb_01\log.txt SIM\tb_ptn\tb_01\command1.txt SIM\tb_ptn\tb_01\command2.txt SIM\tb_ptn\tb_00\din.txt SIM\tb_ptn\tb_00\dout.txt SIM\tb_ptn\tb_00\err.txt SIM\tb_ptn\tb_00\log.txt SIM\tb_ptn\tb_00\command1.txt SIM\tb_ptn\tb_00\command2.txt SIM\tb_ptn\tb_02\din.txt SIM\tb_ptn\tb_02\dout.txt SIM\tb_ptn\tb_02\err.txt SIM\tb_ptn\tb_02\log.txt SIM\tb_ptn\tb_02\command1.txt SIM\tb_ptn\tb_02\command2.txt SIM\tb_ptn\tb_03\din.txt SIM\tb_ptn\tb_03\dout.txt SIM\tb_ptn\tb_03\err.txt SIM\tb_ptn\tb_03\log.txt SIM\tb_ptn\tb_03\command1.txt SIM\tb_ptn\tb_03\command2.txt SIM\tb_ptn\tb_04\din.txt SIM\tb_ptn\tb_04\dout.txt SIM\tb_ptn\tb_04\err.txt SIM\tb_ptn\tb_04\log.txt SIM\tb_ptn\tb_04\command1.txt SIM\tb_ptn\tb_04\command2.txt SIM\tb_ptn\tb_05\din.txt SIM\tb_ptn\tb_05\dout.txt SIM\tb_ptn\tb_05\err.txt SIM\tb_ptn\tb_05\log.txt SIM\tb_ptn\tb_05\command1.txt SIM\tb_ptn\tb_05\command2.txt SIM\tb_ptn\tb_06\din.txt SIM\tb_ptn\tb_06\dout.txt SIM\tb_ptn\tb_06\err.txt SIM\tb_ptn\tb_06\log.txt SIM\tb_ptn\tb_06\command1.txt SIM\tb_ptn\tb_06\command2.txt SIM\tb_ptn\tb_07\din.txt SIM\tb_ptn\tb_07\dout.txt SIM\tb_ptn\tb_07\err.txt SIM\tb_ptn\tb_07\log.txt SIM\tb_ptn\tb_07\command1.txt SIM\tb_ptn\tb_07\command2.txt SIM\tb_ptn\tb_08\din.txt SIM\tb_ptn\tb_08\dout.txt SIM\tb_ptn\tb_08\err.txt SIM\tb_ptn\tb_08\log.txt SIM\tb_ptn\tb_08\command1.txt SIM\tb_ptn\tb_08\command2.txt SIM\tb_ptn\tb_09\din.txt SIM\tb_ptn\tb_09\dout.txt SIM\tb_ptn\tb_09\err.txt SIM\tb_ptn\tb_09\log.txt SIM\tb_ptn\tb_09\command1.txt SIM\tb_ptn\tb_09\command2.txt SIM\tb\tb_vec.vhd SIM\tb\tb_config.vhd SIM\tb\tb_top.VHD SIM\tb\tbclk40.vhd SIM\tb\tbclk66.vhd SIM\compile.do SIM\wave_00.do SIM\vish_stacktrace.vstf SIM\wave_01.do SIM\wave_02.do SIM\wave_03.do SIM\wave_04.do SIM\wave_05.do SIM\wave_06.do SIM\wave_07.do SIM\wave_08.do DOC\examination.xls DOC\嶌惉帒椏\clkblock.vsd DOC\嶌惉帒椏\~$$readtiming2.~vsd DOC\嶌惉帒椏\readblock.vsd DOC\嶌惉帒椏\testbench.vsd DOC\嶌惉帒椏\dpramblock.vsd DOC\嶌惉帒椏\readtiming1.vsd DOC\嶌惉帒椏\writetiming.vsd DOC\嶌惉帒椏\writeblock.vsd DOC\嶌惉帒椏\readtiming2.vsd DOC\嶌惉帒椏\writetimingwr.vsd DOC\嶌惉帒椏\clktiming.vsd DOC\嶌惉帒椏\readtimingwr.vsd DOC\嶌惉帒椏\top1.vsd DOC\嶌惉帒椏\mindeep2.vsd DOC\嶌惉帒椏\rtl.vsd DOC\~$signbook.doc DOC\~WRL3884.tmp DOC\designbook.doc M1\project\xst\dump.xst\toppart.prj\ngx\opt M1\project\xst\dump.xst\toppart.prj\ngx\notopt M1\project\xst\dump.xst\toppart.prj\ngx M1\project\xst\work\sub00 M1\project\xst\dump.xst\toppart.prj M1\project\xst\work M1\project\xst\dump.xst M1\project\_xmsgs M1\project\__projnav M1\project\xst M1\project\_ngo SIM\work\tb_09 SIM\work\tb_08 SIM\work\tb_07 SIM\work\tb_06 SIM\work\tb_05 SIM\work\tb_04 SIM\work\tb_03 SIM\work\tb_02 SIM\work\tb_01 SIM\work\tb_00 SIM\work\tb_vec SIM\work\tbclk40_vec SIM\work\tbclk66_vec SIM\work\tb SIM\work\dpram16b16w SIM\work\clkpart SIM\work\readpart SIM\work\writepart SIM\work\toppart SIM\tb_ptn\tb_01 SIM\tb_ptn\tb_00 SIM\tb_ptn\tb_02 SIM\tb_ptn\tb_03 SIM\tb_ptn\tb_04 SIM\tb_ptn\tb_05 SIM\tb_ptn\tb_06 SIM\tb_ptn\tb_07 SIM\tb_ptn\tb_08 SIM\tb_ptn\tb_09 M1\project M1\macro M1\report M1\bitfile M1\ucf M1\romfile SIM\work SIM\tb_ptn SIM\tb DOC\嶌惉帒椏 M1 RTL SIM DOC