文件名称:async_fifo
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verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
相关搜索： fifo
verilog
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verilog
code
for
fifo
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asynchronous
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Verilog
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verilog
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Verilog
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verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
async_fifo\work\_info
..........\....\.temp\vlognacfvf
..........\....\.....\vlogb5y949
..........\....\_vmake
..........\....\@graycode_@counter\_primary.vhd
..........\....\..................\_primary.dbs
..........\....\..................\_primary.dat
..........\....\..................\verilog.asm
..........\....\..................\verilog.rw
..........\....\async_fifo\_primary.vhd
..........\....\..........\_primary.dbs
..........\....\..........\_primary.dat
..........\....\..........\verilog.asm
..........\....\..........\verilog.rw
..........\....\test_asy_fifo\_primary.vhd
..........\....\.............\_primary.dbs
..........\....\.............\_primary.dat
..........\....\.............\verilog.asm
..........\....\.............\verilog.rw
..........\....\@_opt\vopt3mvfx9
..........\....\.....\vopt056ix9
..........\....\.....\vopte5w5x9
..........\....\.....\vopt3zrcmz
..........\....\.....\voptze3fmz
..........\....\.....\voptszsskz
..........\....\.....\_deps
..........\....\.....\voptwkgmx9
..........\....\.....\voptm57yw9
..........\....\.....\voptimh2x9
..........\....\.....\voptbm68x9
..........\....\.....\vopta456y9
..........\....\.....\vopt7kf9y9
..........\....\.....\voptmf4wkz
..........\....\.....\vopthzezkz
..........\....\.....\voptefs2mz
..........\async_fifo.v
..........\Graycode_Counter.v
..........\restbench.v
..........\Graycode_Counter.v.bak
..........\async_fifo.v.bak
..........\restbench.v.bak
..........\vsim.wlf
..........\wave.do
..........\async_fifo.mpf
..........\async_fifo.cr.mti
..........\work\_temp
..........\....\@graycode_@counter
..........\....\async_fifo
..........\....\test_asy_fifo
..........\....\@_opt
..........\work
async_fifo
..........\....\.temp\vlognacfvf
..........\....\.....\vlogb5y949
..........\....\_vmake
..........\....\@graycode_@counter\_primary.vhd
..........\....\..................\_primary.dbs
..........\....\..................\_primary.dat
..........\....\..................\verilog.asm
..........\....\..................\verilog.rw
..........\....\async_fifo\_primary.vhd
..........\....\..........\_primary.dbs
..........\....\..........\_primary.dat
..........\....\..........\verilog.asm
..........\....\..........\verilog.rw
..........\....\test_asy_fifo\_primary.vhd
..........\....\.............\_primary.dbs
..........\....\.............\_primary.dat
..........\....\.............\verilog.asm
..........\....\.............\verilog.rw
..........\....\@_opt\vopt3mvfx9
..........\....\.....\vopt056ix9
..........\....\.....\vopte5w5x9
..........\....\.....\vopt3zrcmz
..........\....\.....\voptze3fmz
..........\....\.....\voptszsskz
..........\....\.....\_deps
..........\....\.....\voptwkgmx9
..........\....\.....\voptm57yw9
..........\....\.....\voptimh2x9
..........\....\.....\voptbm68x9
..........\....\.....\vopta456y9
..........\....\.....\vopt7kf9y9
..........\....\.....\voptmf4wkz
..........\....\.....\vopthzezkz
..........\....\.....\voptefs2mz
..........\async_fifo.v
..........\Graycode_Counter.v
..........\restbench.v
..........\Graycode_Counter.v.bak
..........\async_fifo.v.bak
..........\restbench.v.bak
..........\vsim.wlf
..........\wave.do
..........\async_fifo.mpf
..........\async_fifo.cr.mti
..........\work\_temp
..........\....\@graycode_@counter
..........\....\async_fifo
..........\....\test_asy_fifo
..........\....\@_opt
..........\work
async_fifo