文件名称:DDRSDRAM_VHDL

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 866kb
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  • 0次
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  • 陈**
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内附doc是DDR SDRAM 参考设计文档;model包含SDRAM VHDL的模型;simulation包含VHDL测试平台、modelsim工程文、设计

库函数;source包含vhdl源文件;synthesis包含工程的综合文件。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM VHDL model simulation with VHDL test bench, modelsim project text, design library function source contains the vhdl source file synthesis comprehensive document that contains the project.
相关搜索: VHDL
DDR
modelsim

(系统自动生成,下载前可以参看下载内容)

下载文件列表

doc\ddr_sdram.pdf

model\mt46v4m16.vhd

.....\mti_pkg.vhd

route\ddr_sdram.csf

.....\ddr_sdram.esf

.....\ddr_sdram.quartus

.....\ddr_sdram.vqm

.....\pll1.vhd

simulation\APEX20KE_MF.VHD

..........\ddr_command.vhd

..........\ddr_control_interface.vhd

..........\ddr_data_path.vhd

..........\ddr_sdram.vhd

..........\ddr_sdram_tb.vhd

..........\io_utils.vhd

..........\lpm_pack.vhd

..........\modelsim.ini

..........\mt46v4m16.vhd

..........\mti_pkg.vhd

..........\pll1.vhd

..........\readme.txt

..........\stdlogar.vhd

..........\util1164.vhd

..........\wave.do

..........\.ork\altcam\behave.dat

..........\....\......\behave.psm

..........\....\......\_primary.dat

..........\....\....lklock\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\...lvds_rx\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\........tx\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\command\rtl.dat

..........\....\.......\rtl.psm

..........\....\.......\_primary.dat

..........\....\..ntrol_interface\rtl.dat

..........\....\.................\rtl.psm

..........\....\.................\_primary.dat

..........\....\ddr_command\rtl.dat

..........\....\...........\rtl.psm

..........\....\...........\_primary.dat

..........\....\......ntrol_interface\rtl.dat

..........\....\.....................\rtl.psm

..........\....\.....................\_primary.dat

..........\....\....data_path\rtl.dat

..........\....\.............\rtl.psm

..........\....\.............\_primary.dat

..........\....\....sdram\rtl.dat

..........\....\.........\rtl.psm

..........\....\.........\_primary.dat

..........\....\........._tb\rtl.dat

..........\....\............\rtl.psm

..........\....\............\_primary.dat

..........\....\io_utils\body.dat

..........\....\........\body.psm

..........\....\........\_primary.dat

..........\....\........\_vhdl.psm

..........\....\lpm_components\body.dat

..........\....\..............\body.psm

..........\....\..............\_primary.dat

..........\....\..............\_vhdl.psm

..........\....\mt46v4m16\behave.dat

..........\....\.........\behave.psm

..........\....\.........\_primary.dat

..........\....\..i_pkg\body.dat

..........\....\.......\body.psm

..........\....\.......\_primary.dat

..........\....\.......\_vhdl.psm

..........\....\pll1\syn.dat

..........\....\....\syn.psm

..........\....\....\_primary.dat

..........\....\std_logic_arith\body.dat

..........\....\...............\body.psm

..........\....\...............\_primary.dat

..........\....\...............\_vhdl.psm

..........\....\util_1164\body.dat

..........\....\.........\body.psm

..........\....\.........\_primary.dat

..........\....\.........\_vhdl.psm

..........\....\_info

.ource\ddr_command.vhd

......\ddr_control_interface.vhd

......\ddr_data_path.vhd

......\ddr_sdram.vhd

.ynthesis\synplicity\ddr_sdram.prj

.........\..........\rev_1\ddr_sdram.srm

.........\..........\.....\ddr_sdram.srr

.........\..........\.....\ddr_sdram.srs

.........\..........\.....\ddr_sdram.tcl

.........\..........\.....\ddr_sdram.tlg

.........\..........\.....\ddr_sdram.vqm

.........\..........\.....\ddr_sdram.xrf

.........\..........\.....\ddr_sdram_cons.tcl

.........\..........\.....\ddr_sdram_rm.tcl

.imulation\work\altcam

..........\....\altclklock

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