文件名称:642_cpld
介绍说明－－下载内容均来自于网络，请自行研究使用
开发DM642系统很好用的cpld程序，包含字符叠加部分-DM642 system, well developed procedures for using cpld, including part of the OSD
(系统自动生成,下载前可以参看下载内容)
下载文件列表
642\db\DM642_Verilog.asm.qmsg
...\..\DM642_Verilog.cbx.xml
...\..\DM642_Verilog.cmp.cdb
...\..\DM642_Verilog.cmp.hdb
...\..\DM642_Verilog.cmp.logdb
...\..\DM642_Verilog.cmp.rdb
...\..\DM642_Verilog.cmp.tdb
...\..\DM642_Verilog.cmp0.ddb
...\..\DM642_Verilog.dbp
...\..\DM642_Verilog.db_info
...\..\DM642_Verilog.eco.cdb
...\..\DM642_Verilog.eds_overflow
...\..\DM642_Verilog.fit.qmsg
...\..\DM642_Verilog.fnsim.cdb
...\..\DM642_Verilog.fnsim.hdb
...\..\DM642_Verilog.fnsim.qmsg
...\..\DM642_Verilog.hier_info
...\..\DM642_Verilog.hif
...\..\DM642_Verilog.map.cdb
...\..\DM642_Verilog.map.hdb
...\..\DM642_Verilog.map.logdb
...\..\DM642_Verilog.map.qmsg
...\..\DM642_Verilog.pre_map.cdb
...\..\DM642_Verilog.pre_map.hdb
...\..\DM642_Verilog.psp
...\..\DM642_Verilog.rtlv.hdb
...\..\DM642_Verilog.rtlv_sg.cdb
...\..\DM642_Verilog.rtlv_sg_swap.cdb
...\..\DM642_Verilog.sgdiff.cdb
...\..\DM642_Verilog.sgdiff.hdb
...\..\DM642_Verilog.sim.hdb
...\..\DM642_Verilog.sim.qmsg
...\..\DM642_Verilog.sim.rdb
...\..\DM642_Verilog.sim.vwf
...\..\DM642_Verilog.sld_design_entry.sci
...\..\DM642_Verilog.sld_design_entry_dsc.sci
...\..\DM642_Verilog.syn_hier_info
...\..\DM642_Verilog.tan.qmsg
...\..\wed.zsf
...\DM642_Verilog.asm.rpt
...\DM642_Verilog.bdf
...\DM642_Verilog.done
...\DM642_Verilog.fit.rpt
...\DM642_Verilog.fit.summary
...\DM642_Verilog.flow.rpt
...\DM642_Verilog.map.rpt
...\DM642_Verilog.map.summary
...\DM642_Verilog.pin
...\DM642_Verilog.pof
...\DM642_Verilog.qpf
...\DM642_Verilog.qsf
...\DM642_Verilog.qws
...\DM642_Verilog.sim.rpt
...\DM642_Verilog.tan.rpt
...\DM642_Verilog.vwf
...\mini_sys.v
...\Waveform1.vwf
...\db
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...\..\DM642_Verilog.cbx.xml
...\..\DM642_Verilog.cmp.cdb
...\..\DM642_Verilog.cmp.hdb
...\..\DM642_Verilog.cmp.logdb
...\..\DM642_Verilog.cmp.rdb
...\..\DM642_Verilog.cmp.tdb
...\..\DM642_Verilog.cmp0.ddb
...\..\DM642_Verilog.dbp
...\..\DM642_Verilog.db_info
...\..\DM642_Verilog.eco.cdb
...\..\DM642_Verilog.eds_overflow
...\..\DM642_Verilog.fit.qmsg
...\..\DM642_Verilog.fnsim.cdb
...\..\DM642_Verilog.fnsim.hdb
...\..\DM642_Verilog.fnsim.qmsg
...\..\DM642_Verilog.hier_info
...\..\DM642_Verilog.hif
...\..\DM642_Verilog.map.cdb
...\..\DM642_Verilog.map.hdb
...\..\DM642_Verilog.map.logdb
...\..\DM642_Verilog.map.qmsg
...\..\DM642_Verilog.pre_map.cdb
...\..\DM642_Verilog.pre_map.hdb
...\..\DM642_Verilog.psp
...\..\DM642_Verilog.rtlv.hdb
...\..\DM642_Verilog.rtlv_sg.cdb
...\..\DM642_Verilog.rtlv_sg_swap.cdb
...\..\DM642_Verilog.sgdiff.cdb
...\..\DM642_Verilog.sgdiff.hdb
...\..\DM642_Verilog.sim.hdb
...\..\DM642_Verilog.sim.qmsg
...\..\DM642_Verilog.sim.rdb
...\..\DM642_Verilog.sim.vwf
...\..\DM642_Verilog.sld_design_entry.sci
...\..\DM642_Verilog.sld_design_entry_dsc.sci
...\..\DM642_Verilog.syn_hier_info
...\..\DM642_Verilog.tan.qmsg
...\..\wed.zsf
...\DM642_Verilog.asm.rpt
...\DM642_Verilog.bdf
...\DM642_Verilog.done
...\DM642_Verilog.fit.rpt
...\DM642_Verilog.fit.summary
...\DM642_Verilog.flow.rpt
...\DM642_Verilog.map.rpt
...\DM642_Verilog.map.summary
...\DM642_Verilog.pin
...\DM642_Verilog.pof
...\DM642_Verilog.qpf
...\DM642_Verilog.qsf
...\DM642_Verilog.qws
...\DM642_Verilog.sim.rpt
...\DM642_Verilog.tan.rpt
...\DM642_Verilog.vwf
...\mini_sys.v
...\Waveform1.vwf
...\db
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