文件名称:DDRSDRAM_MT46V32M16TG

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 536kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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ddr控制器 对DDR实现读写控制-ddr control
(系统自动生成,下载前可以参看下载内容)

下载文件列表

board_files\DDR_SDRAM

...........\.........\Readme.txt

...........\.........\Syn

...........\.........\...\syn_vhd_bl4cl2

...........\.........\...\..............\datasheet.txt

...........\.........\...\..............\ddr.cpj

...........\.........\...\..............\par

...........\.........\...\..............\...\ddr.cdc

...........\.........\...\..............\...\mem_interface_top.bit

...........\.........\...\..............\...\mem_interface_top.edf

...........\.........\...\..............\...\mem_interface_top.ucf

...........\.........\...\..............\...\par.ise

...........\.........\...\..............\...\Readme.txt

...........\.........\...\..............\Readme.txt

...........\.........\...\..............\rtl

...........\.........\...\..............\...\mem_interface_top.vhd

...........\.........\...\..............\...\mem_interface_top_addr_gen_0.vhd

...........\.........\...\..............\...\mem_interface_top_cal_ctl_0.vhd

...........\.........\...\..............\...\mem_interface_top_cal_top.vhd

...........\.........\...\..............\...\mem_interface_top_clk_dcm.vhd

...........\.........\...\..............\...\mem_interface_top_cmd_fsm_0.vhd

...........\.........\...\..............\...\mem_interface_top_cmp_data_0.vhd

...........\.........\...\..............\...\mem_interface_top_controller_0.vhd

...........\.........\...\..............\...\mem_interface_top_controller_iobs_0.vhd

...........\.........\...\..............\...\mem_interface_top_data_path_0.vhd

...........\.........\...\..............\...\mem_interface_top_data_path_iobs_0.vhd

...........\.........\...\..............\...\mem_interface_top_data_path_rst.vhd

...........\.........\...\..............\...\mem_interface_top_data_read_0.vhd

...........\.........\...\..............\...\mem_interface_top_data_read_controller_0.vhd

...........\.........\...\..............\...\mem_interface_top_data_write_0.vhd

...........\.........\...\..............\...\mem_interface_top_ddr1_dm_0.vhd

...........\.........\...\..............\...\mem_interface_top_ddr1_test_bench_0.vhd

...........\.........\...\..............\...\mem_interface_top_dqs_delay_0.vhd

...........\.........\...\..............\...\mem_interface_top_fifo_0_wr_en_0.vhd

...........\.........\...\..............\...\mem_interface_top_fifo_1_wr_en_0.vhd

...........\.........\...\..............\...\mem_interface_top_infrastructure.vhd

...........\.........\...\..............\...\mem_interface_top_infrastructure_iobs_0.vhd

...........\.........\...\..............\...\mem_interface_top_infrastructure_top_0.vhd

...........\.........\...\..............\...\mem_interface_top_iobs_0.vhd

...........\.........\...\..............\...\mem_interface_top_lfsr32_0.vhd

...........\.........\...\..............\...\mem_interface_top_main_0.vhd

...........\.........\...\..............\...\mem_interface_top_parameters_0.vhd

...........\.........\...\..............\...\mem_interface_top_RAM8D_0.vhd

...........\.........\...\..............\...\mem_interface_top_RAM8D_1.vhd

...........\.........\...\..............\...\mem_interface_top_rd_gray_cntr.vhd

...........\.........\...\..............\...\mem_interface_top_s3_ddr_iob.vhd

...........\.........\...\..............\...\mem_interface_top_s3_dqs_iob.vhd

...........\.........\...\..............\...\mem_interface_top_tap_dly_0.vhd

...........\.........\...\..............\...\mem_interface_top_top_0.vhd

...........\.........\...\..............\...\mem_interface_top_wr_gray_cntr.vhd

...........\.........\...\..............\sim

...........\.........\...\..............\...\ddr.v

...........\.........\...\..............\...\ddr1_test_tb.v

...........\.........\...\..............\...\ddr_parameters.vh

...........\.........\...\..............\...\glbl.v

...........\.........\...\..............\...\parameters.v

...........\.........\...\..............\...\readme.txt

...........\.........\...\..............\synth

...........\.........\...\..............\.....\mem_interface_top.lso

...........\.........\...\..............\.....\mem_interface_top.prj

...........\.........\...\

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