文件名称:DDRcontroller

  • 所属分类:
  • 软件工程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 782kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 张*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
相关搜索: Verilog
DDR

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR设计参考说明及代码\doc\ddr_sdram.pdf

.....................\model\mt46v4m16.v

.....................\readme.txt

.....................\.oute\ddr_sdram.csf

.....................\.....\ddr_sdram.esf

.....................\.....\ddr_sdram.psf

.....................\.....\ddr_sdram.quartus

.....................\.....\ddr_sdram.vqm

.....................\.....\pll1.v

.....................\simulation\ddr_compile_all.v

.....................\..........\ddr_sdram_tb.v

.....................\..........\modelsim.ini

.....................\..........\readme.txt

.....................\..........\work\altclklock\verilog.psm

.....................\..........\....\..........\_primary.dat

.....................\..........\....\..........\_primary.vhd

.....................\..........\....\ddr_command\verilog.psm

.....................\..........\....\...........\_primary.dat

.....................\..........\....\...........\_primary.vhd

.....................\..........\....\......ntrol_interface\verilog.psm

.....................\..........\....\.....................\_primary.dat

.....................\..........\....\.....................\_primary.vhd

.....................\..........\....\....data_path\verilog.psm

.....................\..........\....\.............\_primary.dat

.....................\..........\....\.............\_primary.vhd

.....................\..........\....\....sdram\verilog.psm

.....................\..........\....\.........\_primary.dat

.....................\..........\....\.........\_primary.vhd

.....................\..........\....\........._tb\verilog.psm

.....................\..........\....\............\_primary.dat

.....................\..........\....\............\_primary.vhd

.....................\..........\....\mt46v4m16\verilog.psm

.....................\..........\....\.........\_primary.dat

.....................\..........\....\.........\_primary.vhd

.....................\..........\....\pll1\verilog.psm

.....................\..........\....\....\_primary.dat

.....................\..........\....\....\_primary.vhd

.....................\..........\....\_info

.....................\.ource\altclklock.v

.....................\......\ddr_Command.v

.....................\......\ddr_control_interface.v

.....................\......\ddr_data_path.v

.....................\......\ddr_sdram.v

.....................\......\Params.v

.....................\......\pll1.v

.....................\.ynthesis\synplicity\ddr_data_path.srm

.....................\.........\..........\ddr_data_path.srr

.....................\.........\..........\ddr_data_path.srs

.....................\.........\..........\ddr_data_path.tlg

.....................\.........\..........\ddr_data_path.xrf

.....................\.........\..........\ddr_sdram.prj

.....................\.........\..........\ddr_sdram.sdc

.....................\.........\..........\ddr_sdram.srm

.....................\.........\..........\ddr_sdram.srr

.....................\.........\..........\ddr_sdram.srs

.....................\.........\..........\ddr_sdram.tcl

.....................\.........\..........\ddr_sdram.tlg

.....................\.........\..........\ddr_sdram.vqm

.....................\.........\..........\ddr_sdram.xrf

.....................\.........\..........\ddr_sdram_cons.tcl

.....................\.........\..........\ddr_sdram_rm.tcl

.....................\wp_ddr_sdram_upgrade.pdf

.....................\simulation\work\altclklock

.....................\..........\....\ddr_command

.....................\..........\....\ddr_control_interface

.....................\..........\....\ddr_data_path

.....................\..........\....\ddr_sdram

.....................\..........\....\ddr_sdram_tb

.....................\..........\....\mt46v4m16

.....................\..........\....\pll1

.....................\..........\work

.....................\.ynthesis\synplicity

.....................\doc

.....................\model

.....................\route

.....................\simulation

.....................\source

.....................\synthesis

DDR设计参考说明及代码

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org