文件名称:ramtest
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog语言往内部FPGA的sram中读写数据，即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ramtest\2.v
.......\automake.log
.......\coregen.log
.......\coregen.prj
.......\ramtest.cmd_log
.......\ramtest.dhp
.......\ramtest.lso
.......\ramtest.ngc
.......\ramtest.ngr
.......\ramtest.npl
.......\ramtest.prj
.......\ramtest.stx
.......\ramtest.syr
.......\ramtest.v
.......\ramtest_m.v
.......\ramtest_m.v.bak
.......\ramtest_m2.v
.......\ramtest_m3.v
.......\ramtest_ramtest_m2_v_tf.fdo
.......\ramtest_ramtest_m2_v_tf.udo
.......\ramtest_ramtest_m3_v_tf.fdo
.......\ramtest_ramtest_m3_v_tf.udo
.......\ramtest_ramtest_m_v_tf.fdo
.......\ramtest_ramtest_m_v_tf.udo
.......\ramtest_ramtest_t_v_tf.fdo
.......\ramtest_ramtest_t_v_tf.udo
.......\ramtest_t.v
.......\ramtest_t.v.bak
.......\ramtest_vhdl.prj
.......\transcript
.......\vsim.wlf
.......\work\glbl\verilog.asm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\glbl
.......\....\ramtest\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\ramtest
.......\....\......._ramtest_m2_v_tf\verilog.asm
.......\....\.......................\_primary.dat
.......\....\.......................\_primary.vhd
.......\....\ramtest_ramtest_m2_v_tf
.......\....\.................3_v_tf\verilog.asm
.......\....\.......................\_primary.dat
.......\....\.......................\_primary.vhd
.......\....\ramtest_ramtest_m3_v_tf
.......\....\................._v_tf\verilog.asm
.......\....\......................\_primary.dat
.......\....\......................\_primary.vhd
.......\....\ramtest_ramtest_m_v_tf
.......\....\_info
.......\work
.......\xst\work\hdllib.ref
.......\...\....\vlg68\ramtest.bin
.......\...\....\vlg68
.......\...\work
.......\xst
.......\__projnav\coregen.rsp
.......\.........\createTF.err
.......\.........\ramtest.gfl
.......\.........\ramtest.xst
.......\.........\ramtest_flowplus.gfl
.......\.........\runXst_tcl.rsp
.......\__projnav
.......\__projnav.log
ramtest
.......\automake.log
.......\coregen.log
.......\coregen.prj
.......\ramtest.cmd_log
.......\ramtest.dhp
.......\ramtest.lso
.......\ramtest.ngc
.......\ramtest.ngr
.......\ramtest.npl
.......\ramtest.prj
.......\ramtest.stx
.......\ramtest.syr
.......\ramtest.v
.......\ramtest_m.v
.......\ramtest_m.v.bak
.......\ramtest_m2.v
.......\ramtest_m3.v
.......\ramtest_ramtest_m2_v_tf.fdo
.......\ramtest_ramtest_m2_v_tf.udo
.......\ramtest_ramtest_m3_v_tf.fdo
.......\ramtest_ramtest_m3_v_tf.udo
.......\ramtest_ramtest_m_v_tf.fdo
.......\ramtest_ramtest_m_v_tf.udo
.......\ramtest_ramtest_t_v_tf.fdo
.......\ramtest_ramtest_t_v_tf.udo
.......\ramtest_t.v
.......\ramtest_t.v.bak
.......\ramtest_vhdl.prj
.......\transcript
.......\vsim.wlf
.......\work\glbl\verilog.asm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\glbl
.......\....\ramtest\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\ramtest
.......\....\......._ramtest_m2_v_tf\verilog.asm
.......\....\.......................\_primary.dat
.......\....\.......................\_primary.vhd
.......\....\ramtest_ramtest_m2_v_tf
.......\....\.................3_v_tf\verilog.asm
.......\....\.......................\_primary.dat
.......\....\.......................\_primary.vhd
.......\....\ramtest_ramtest_m3_v_tf
.......\....\................._v_tf\verilog.asm
.......\....\......................\_primary.dat
.......\....\......................\_primary.vhd
.......\....\ramtest_ramtest_m_v_tf
.......\....\_info
.......\work
.......\xst\work\hdllib.ref
.......\...\....\vlg68\ramtest.bin
.......\...\....\vlg68
.......\...\work
.......\xst
.......\__projnav\coregen.rsp
.......\.........\createTF.err
.......\.........\ramtest.gfl
.......\.........\ramtest.xst
.......\.........\ramtest_flowplus.gfl
.......\.........\runXst_tcl.rsp
.......\__projnav
.......\__projnav.log
ramtest