文件名称:ASIC
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本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从
设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of system-level behavioral descr iptions or RTL descr iption of the beginning, followed by behavioral-level functional verification system, design an integrated, comprehensive post-simulation, automatic placement and routing to the final post-layout simulation. In
设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of system-level behavioral descr iptions or RTL descr iption of the beginning, followed by behavioral-level functional verification system, design an integrated, comprehensive post-simulation, automatic placement and routing to the final post-layout simulation. In
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下载文件列表
一个ASIC设计流程实例.pdf
readme.txt
readme.txt