文件名称:mcode_FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
伪随机码发生器，次源码已经经过了测试并通过时序仿真验证没有任何问题，此小m序列发生器的特征多项式我没有写，但我建议大家在看原代码之前还是先看下扩频通信中m、M、Gold序列的原理，只有这样才能够真正的明白伪随机码发生器发生器的原理。-mcode_FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mcode_FPGA\mcode_FPGA.qpf
..........\mcode_FPGA.qsf
..........\db\mux_aoc.tdf
..........\..\mcode_FPGA.db_info
..........\..\mcode_FPGA.fit.qmsg
..........\..\mcode_FPGA.map_bb.logdb
..........\..\mcode_FPGA.tis_db_list.ddb
..........\..\mcode_FPGA.asm.qmsg
..........\..\cntr_aai.tdf
..........\..\cmpr_7cc.tdf
..........\..\mcode_FPGA.cbx.xml
..........\..\mcode_FPGA.hif
..........\..\prev_cmp_mcode_FPGA.qmsg
..........\..\mcode_FPGA.map.qmsg
..........\..\mcode_FPGA.sim.qmsg
..........\..\prev_cmp_mcode_FPGA.sim.qmsg
..........\..\mcode_FPGA.map_bb.hdbx
..........\..\mcode_FPGA.tan.qmsg
..........\..\mcode_FPGA.cmp.cdb
..........\..\mcode_FPGA.fnsim.qmsg
..........\..\mcode_FPGA.sim.hdb
..........\..\mcode_FPGA.cmp.logdb
..........\..\mcode_FPGA.sim.cvwf
..........\..\mcode_FPGA.rtlv_sg.cdb
..........\..\mcode_FPGA.sim.rdb
..........\..\prev_cmp_mcode_FPGA.map.qmsg
..........\..\mcode_FPGA.sgdiff.hdb
..........\..\mcode_FPGA.pre_map.cdb
..........\..\mcode_FPGA.eco.cdb
..........\..\mcode_FPGA.sgdiff.cdb
..........\..\prev_cmp_mcode_FPGA.fit.qmsg
..........\..\prev_cmp_mcode_FPGA.asm.qmsg
..........\..\mcode_FPGA.rtlv.hdb
..........\..\mcode_FPGA.hier_info
..........\..\mcode_FPGA.cmp.ecobp
..........\..\mcode_FPGA.pre_map.hdb
..........\..\prev_cmp_mcode_FPGA.tan.qmsg
..........\..\mcode_FPGA.fnsim.hdb
..........\..\mcode_FPGA.psp
..........\..\mcode_FPGA.sld_design_entry_dsc.sci
..........\..\cntr_02j.tdf
..........\..\cntr_sbi.tdf
..........\..\mcode_FPGA.simfam
..........\..\cmpr_8cc.tdf
..........\..\cntr_gui.tdf
..........\..\cmpr_5cc.tdf
..........\..\mcode_FPGA.cmp.bpm
..........\..\altsyncram_k1p3.tdf
..........\..\decode_rqf.tdf
..........\..\mcode_FPGA.rtlv_sg_swap.cdb
..........\..\mcode_FPGA.syn_hier_info
..........\..\mcode_FPGA.map.ecobp
..........\..\mcode_FPGA.map.kpt
..........\..\mcode_FPGA.cmp_merge.kpt
..........\..\mcode_FPGA.cmp.kpt
..........\..\mcode_FPGA.map_bb.cdb
..........\..\mcode_FPGA.map_bb.hdb
..........\..\mcode_FPGA.map.cdb
..........\..\mcode_FPGA.map.hdb
..........\..\mcode_FPGA.map.logdb
..........\..\mcode_FPGA.map.bpm
..........\..\mcode_FPGA.asm_labs.ddb
..........\..\mcode_FPGA.cmp.hdb
..........\..\mcode_FPGA.cmp.tdb
..........\..\mcode_FPGA.sld_design_entry.sci
..........\..\mcode_FPGA.cmp.rdb
..........\..\mcode_FPGA.cmp0.ddb
..........\..\wed.wsf
..........\..\mcode_FPGA.eds_overflow
..........\code.v
..........\stp1.stp
..........\mcode_FPGA.map.summary
..........\mcode_FPGA.map.rpt
..........\mcode_FPGA.flow.rpt
..........\code.v.bak
..........\mcode_FPGA.bdf
..........\code1.bsf
..........\mcode_FPGA.done
..........\incremental_db\compiled_partitions\mcode_FPGA.root_partition.map.kpt
..........\..............\...................\mcode_FPGA.root_partition.map.atm
..........\..............\...................\mcode_FPGA.root_partition.map.hdbx
..........\..............\...................\mcode_FPGA.root_partition.cmp.rcf
..........\..............\...................\mcode_FPGA.root_partition.cmp.hdbx
..........\..............\...................\mcode_FPGA.root_partition.cmp.atm
..........\..............\...................\mcode_FPGA.root_partition.cmp.logdb
..........\..............\...................\mcode_FPGA.root_partition.cmp.kpt
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
..........\..............\...................\mcode_FPGA.root_partition.map.dpi
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi
..........\..............\............
..........\mcode_FPGA.qsf
..........\db\mux_aoc.tdf
..........\..\mcode_FPGA.db_info
..........\..\mcode_FPGA.fit.qmsg
..........\..\mcode_FPGA.map_bb.logdb
..........\..\mcode_FPGA.tis_db_list.ddb
..........\..\mcode_FPGA.asm.qmsg
..........\..\cntr_aai.tdf
..........\..\cmpr_7cc.tdf
..........\..\mcode_FPGA.cbx.xml
..........\..\mcode_FPGA.hif
..........\..\prev_cmp_mcode_FPGA.qmsg
..........\..\mcode_FPGA.map.qmsg
..........\..\mcode_FPGA.sim.qmsg
..........\..\prev_cmp_mcode_FPGA.sim.qmsg
..........\..\mcode_FPGA.map_bb.hdbx
..........\..\mcode_FPGA.tan.qmsg
..........\..\mcode_FPGA.cmp.cdb
..........\..\mcode_FPGA.fnsim.qmsg
..........\..\mcode_FPGA.sim.hdb
..........\..\mcode_FPGA.cmp.logdb
..........\..\mcode_FPGA.sim.cvwf
..........\..\mcode_FPGA.rtlv_sg.cdb
..........\..\mcode_FPGA.sim.rdb
..........\..\prev_cmp_mcode_FPGA.map.qmsg
..........\..\mcode_FPGA.sgdiff.hdb
..........\..\mcode_FPGA.pre_map.cdb
..........\..\mcode_FPGA.eco.cdb
..........\..\mcode_FPGA.sgdiff.cdb
..........\..\prev_cmp_mcode_FPGA.fit.qmsg
..........\..\prev_cmp_mcode_FPGA.asm.qmsg
..........\..\mcode_FPGA.rtlv.hdb
..........\..\mcode_FPGA.hier_info
..........\..\mcode_FPGA.cmp.ecobp
..........\..\mcode_FPGA.pre_map.hdb
..........\..\prev_cmp_mcode_FPGA.tan.qmsg
..........\..\mcode_FPGA.fnsim.hdb
..........\..\mcode_FPGA.psp
..........\..\mcode_FPGA.sld_design_entry_dsc.sci
..........\..\cntr_02j.tdf
..........\..\cntr_sbi.tdf
..........\..\mcode_FPGA.simfam
..........\..\cmpr_8cc.tdf
..........\..\cntr_gui.tdf
..........\..\cmpr_5cc.tdf
..........\..\mcode_FPGA.cmp.bpm
..........\..\altsyncram_k1p3.tdf
..........\..\decode_rqf.tdf
..........\..\mcode_FPGA.rtlv_sg_swap.cdb
..........\..\mcode_FPGA.syn_hier_info
..........\..\mcode_FPGA.map.ecobp
..........\..\mcode_FPGA.map.kpt
..........\..\mcode_FPGA.cmp_merge.kpt
..........\..\mcode_FPGA.cmp.kpt
..........\..\mcode_FPGA.map_bb.cdb
..........\..\mcode_FPGA.map_bb.hdb
..........\..\mcode_FPGA.map.cdb
..........\..\mcode_FPGA.map.hdb
..........\..\mcode_FPGA.map.logdb
..........\..\mcode_FPGA.map.bpm
..........\..\mcode_FPGA.asm_labs.ddb
..........\..\mcode_FPGA.cmp.hdb
..........\..\mcode_FPGA.cmp.tdb
..........\..\mcode_FPGA.sld_design_entry.sci
..........\..\mcode_FPGA.cmp.rdb
..........\..\mcode_FPGA.cmp0.ddb
..........\..\wed.wsf
..........\..\mcode_FPGA.eds_overflow
..........\code.v
..........\stp1.stp
..........\mcode_FPGA.map.summary
..........\mcode_FPGA.map.rpt
..........\mcode_FPGA.flow.rpt
..........\code.v.bak
..........\mcode_FPGA.bdf
..........\code1.bsf
..........\mcode_FPGA.done
..........\incremental_db\compiled_partitions\mcode_FPGA.root_partition.map.kpt
..........\..............\...................\mcode_FPGA.root_partition.map.atm
..........\..............\...................\mcode_FPGA.root_partition.map.hdbx
..........\..............\...................\mcode_FPGA.root_partition.cmp.rcf
..........\..............\...................\mcode_FPGA.root_partition.cmp.hdbx
..........\..............\...................\mcode_FPGA.root_partition.cmp.atm
..........\..............\...................\mcode_FPGA.root_partition.cmp.logdb
..........\..............\...................\mcode_FPGA.root_partition.cmp.kpt
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.kpt
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm
..........\..............\...................\mcode_FPGA.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.hdbx
..........\..............\...................\mcode_FPGA.root_partition.map.dpi
..........\..............\...................\mcode_FPGA.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.dpi
..........\..............\............