文件名称:ASK_modulator
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振幅键控ASK的调制解调Verilog实现，带测试文件-ASK amplitude shift keying modulation and demodulation Verilog implementation, with the test file
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下载文件列表
ASK_modulator
.............\ASK.cr.mti
.............\ASK.mpf
.............\ASK_demodulator.v
.............\ASK_demodulator.v.bak
.............\ASK_modulator.v
.............\ASK_modulator.v.bak
.............\test.v
.............\test.v.bak
.............\vsim.wlf
.............\work
.............\....\@a@s@k_demodulator
.............\....\..................\verilog.asm
.............\....\..................\verilog.rw
.............\....\..................\_primary.dat
.............\....\..................\_primary.dbs
.............\....\..................\_primary.vhd
.............\....\@a@s@k_modulator
.............\....\................\verilog.asm
.............\....\................\verilog.rw
.............\....\................\_primary.dat
.............\....\................\_primary.dbs
.............\....\................\_primary.vhd
.............\....\test
.............\....\....\verilog.asm
.............\....\....\verilog.rw
.............\....\....\_primary.dat
.............\....\....\_primary.dbs
.............\....\....\_primary.vhd
.............\....\_info
.............\....\_temp
.............\....\.....\vlog1c5qh6
.............\....\.....\vlog604zv0
.............\....\.....\vlogdtb33w
.............\....\.....\vlogfj9c78
.............\....\.....\vloggfwyjb
.............\....\.....\vloggiayih
.............\....\.....\vlogh0mdqt
.............\....\.....\vlogz09r2w
.............\....\_vmake
.............\ASK.cr.mti
.............\ASK.mpf
.............\ASK_demodulator.v
.............\ASK_demodulator.v.bak
.............\ASK_modulator.v
.............\ASK_modulator.v.bak
.............\test.v
.............\test.v.bak
.............\vsim.wlf
.............\work
.............\....\@a@s@k_demodulator
.............\....\..................\verilog.asm
.............\....\..................\verilog.rw
.............\....\..................\_primary.dat
.............\....\..................\_primary.dbs
.............\....\..................\_primary.vhd
.............\....\@a@s@k_modulator
.............\....\................\verilog.asm
.............\....\................\verilog.rw
.............\....\................\_primary.dat
.............\....\................\_primary.dbs
.............\....\................\_primary.vhd
.............\....\test
.............\....\....\verilog.asm
.............\....\....\verilog.rw
.............\....\....\_primary.dat
.............\....\....\_primary.dbs
.............\....\....\_primary.vhd
.............\....\_info
.............\....\_temp
.............\....\.....\vlog1c5qh6
.............\....\.....\vlog604zv0
.............\....\.....\vlogdtb33w
.............\....\.....\vlogfj9c78
.............\....\.....\vloggfwyjb
.............\....\.....\vloggiayih
.............\....\.....\vlogh0mdqt
.............\....\.....\vlogz09r2w
.............\....\_vmake