文件名称:riscmcu
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精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
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下载文件列表
压缩包 : 75448163riscmcu.rar 列表 riscmcu\work\_info riscmcu\work\clk_gen\_primary.vhd riscmcu\work\clk_gen\verilog.asm riscmcu\work\clk_gen\_primary.dat riscmcu\work\clk_gen riscmcu\work\register\_primary.vhd riscmcu\work\register\verilog.asm riscmcu\work\register\_primary.dat riscmcu\work\register riscmcu\work\accum\_primary.vhd riscmcu\work\accum\verilog.asm riscmcu\work\accum\_primary.dat riscmcu\work\accum riscmcu\work\datact1\_primary.vhd riscmcu\work\datact1\verilog.asm riscmcu\work\datact1\_primary.dat riscmcu\work\datact1 riscmcu\work\adr\_primary.vhd riscmcu\work\adr\verilog.asm riscmcu\work\adr\_primary.dat riscmcu\work\adr riscmcu\work\counter\_primary.vhd riscmcu\work\counter\verilog.asm riscmcu\work\counter\_primary.dat riscmcu\work\counter riscmcu\work\machinect1\_primary.vhd riscmcu\work\machinect1\verilog.asm riscmcu\work\machinect1\_primary.dat riscmcu\work\machinect1 riscmcu\work\addr_decode\_primary.vhd riscmcu\work\addr_decode\verilog.asm riscmcu\work\addr_decode\_primary.dat riscmcu\work\addr_decode riscmcu\work\ram\_primary.vhd riscmcu\work\ram\verilog.asm riscmcu\work\ram\_primary.dat riscmcu\work\ram riscmcu\work\rom\_primary.vhd riscmcu\work\rom\verilog.asm riscmcu\work\rom\_primary.dat riscmcu\work\rom riscmcu\work\alu\_primary.vhd riscmcu\work\alu\verilog.asm riscmcu\work\alu\_primary.dat riscmcu\work\alu riscmcu\work\machine\_primary.vhd riscmcu\work\machine\verilog.asm riscmcu\work\machine\_primary.dat riscmcu\work\machine riscmcu\work\riscmcu\_primary.vhd riscmcu\work\riscmcu\verilog.asm riscmcu\work\riscmcu\_primary.dat riscmcu\work\riscmcu riscmcu\work riscmcu\riscmcu.cr.mti riscmcu\transcript riscmcu\rom_data riscmcu\vsim.wlf riscmcu\riscmcu.wlf riscmcu\wave.do riscmcu\vish_stacktrace.vstf riscmcu\ram.v.bak riscmcu\riscmcu.mpf riscmcu\RISCCPU.doc riscmcu\riscmcu.v riscmcu\clk_gen.v riscmcu\clk_gen.v.bak riscmcu\register.v riscmcu\register.v.bak riscmcu\accum.v riscmcu\accum.v.bak riscmcu\alu.v riscmcu\alu.v.bak riscmcu\datact1.v riscmcu\datact1.v.bak riscmcu\adr.v riscmcu\adr.v.bak riscmcu\counter.v riscmcu\counter.v.bak riscmcu\machinect1.v riscmcu\machinect1.v.bak riscmcu\machine.v riscmcu\machine.v.bak riscmcu\addr_decode.v riscmcu\addr_decode.v.bak riscmcu\ram.v riscmcu\rom.v riscmcu\rom.v.bak riscmcu\riscmcu.v.bak riscmcu