文件名称:TCNTL
介绍说明－－下载内容均来自于网络，请自行研究使用
用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 13898396tcntl.rar 列表 TCNTL\.lso TCNTL\genExpectedResults.cmd TCNTL\isim\simprim_ver.auxlib\ffsrce\ffsrce.h TCNTL\isim\simprim_ver.auxlib\ffsrce\mingw\ffsrce.obj TCNTL\isim\simprim_ver.auxlib\hdllib.ref TCNTL\isim\simprim_ver.auxlib\_x___b_u_f\mingw\_x___b_u_f.obj TCNTL\isim\simprim_ver.auxlib\_x___b_u_f\_x___b_u_f.h TCNTL\isim\simprim_ver.auxlib\_x___b_u_f_g_m_u_x\mingw\_x___b_u_f_g_m_u_x.obj TCNTL\isim\simprim_ver.auxlib\_x___b_u_f_g_m_u_x\_x___b_u_f_g_m_u_x.h TCNTL\isim\simprim_ver.auxlib\_x___f_f\mingw\_x___f_f.obj TCNTL\isim\simprim_ver.auxlib\_x___f_f\_x___f_f.h TCNTL\isim\simprim_ver.auxlib\_x___i_n_v\mingw\_x___i_n_v.obj TCNTL\isim\simprim_ver.auxlib\_x___i_n_v\_x___i_n_v.h TCNTL\isim\simprim_ver.auxlib\_x___i_p_a_d\mingw\_x___i_p_a_d.obj TCNTL\isim\simprim_ver.auxlib\_x___i_p_a_d\_x___i_p_a_d.h TCNTL\isim\simprim_ver.auxlib\_x___l_u_t4\mingw\_x___l_u_t4.obj TCNTL\isim\simprim_ver.auxlib\_x___l_u_t4\_x___l_u_t4.h TCNTL\isim\simprim_ver.auxlib\_x___o_b_u_f\mingw\_x___o_b_u_f.obj TCNTL\isim\simprim_ver.auxlib\_x___o_b_u_f\_x___o_b_u_f.h TCNTL\isim\simprim_ver.auxlib\_x___o_n_e\mingw\_x___o_n_e.obj TCNTL\isim\simprim_ver.auxlib\_x___o_n_e\_x___o_n_e.h TCNTL\isim\simprim_ver.auxlib\_x___o_p_a_d\mingw\_x___o_p_a_d.obj TCNTL\isim\simprim_ver.auxlib\_x___o_p_a_d\_x___o_p_a_d.h TCNTL\isim\simprim_ver.auxlib\_x___z_e_r_o\mingw\_x___z_e_r_o.obj TCNTL\isim\simprim_ver.auxlib\_x___z_e_r_o\_x___z_e_r_o.h TCNTL\isim\work\glbl\glbl.h TCNTL\isim\work\glbl\mingw\glbl.obj TCNTL\isim\work\hdllib.ref TCNTL\isim\work\hdpdeps.ref TCNTL\isim\work\sub00\vhpl00.vho TCNTL\isim\work\sub00\vhpl01.vho TCNTL\isim\work\sub00\vhpl02.vho TCNTL\isim\work\sub00\vhpl03.vho TCNTL\isim\work\tcntl\behavior.h TCNTL\isim\work\tcntl\mingw\behavior.obj TCNTL\isim\work\tcntl_tb\mingw\testbench_arch.obj TCNTL\isim\work\tcntl_tb\testbench_arch.h TCNTL\isim\work\tcntl_tb\xsimtestbench_arch.cpp TCNTL\isim\work\vlg2D\glbl.bin TCNTL\isim\work\vlg59\_t_c_n_t_l.bin TCNTL\isim\work\_t_c_n_t_l\mingw\_t_c_n_t_l.obj TCNTL\isim\work\_t_c_n_t_l\_t_c_n_t_l.h TCNTL\isim.cmd TCNTL\isim.hdlsourcefiles TCNTL\isim.log TCNTL\isim.tmp_save\_1 TCNTL\isimwavedata.xwv TCNTL\netgen\par\TCNTL_timesim.nlf TCNTL\netgen\par\tcntl_timesim.sdf TCNTL\netgen\par\TCNTL_timesim.v TCNTL\netgen\synthesis\TCNTL_synthesis.nlf TCNTL\netgen\synthesis\TCNTL_synthesis.v TCNTL\pepExtractor.prj TCNTL\TCNTL.bld TCNTL\TCNTL.cmd_log TCNTL\TCNTL.ise TCNTL\TCNTL.ise_ISE_Backup TCNTL\TCNTL.lso TCNTL\TCNTL.ncd TCNTL\TCNTL.ngc TCNTL\TCNTL.ngd TCNTL\TCNTL.ngr TCNTL\TCNTL.ntrc_log TCNTL\TCNTL.pad TCNTL\TCNTL.par TCNTL\TCNTL.pcf TCNTL\TCNTL.prj TCNTL\TCNTL.stx TCNTL\TCNTL.syr TCNTL\tcntl.twr TCNTL\tcntl.twx TCNTL\TCNTL.unroutes TCNTL\TCNTL.vhd TCNTL\TCNTL.xpi TCNTL\TCNTL.xst TCNTL\TCNTL_map.mrp TCNTL\TCNTL_map.ncd TCNTL\TCNTL_map.ngm TCNTL\TCNTL_pad.csv TCNTL\TCNTL_pad.txt TCNTL\TCNTL_prev_built.ngd TCNTL\TCNTL_summary.html TCNTL\TCNTL_tb.ano TCNTL\TCNTL_tb.ant TCNTL\TCNTL_tb.jhd TCNTL\TCNTL_tb.tbw TCNTL\TCNTL_tb.vhw TCNTL\TCNTL_tb.xwv TCNTL\TCNTL_tb.xwv_bak TCNTL\TCNTL_tb_bencher.prj TCNTL\TCNTL_tb_gen.prj TCNTL\TCNTL_tb_isim_par.exe TCNTL\TCNTL_tb_par.prj TCNTL\TCNTL_tb_tbxr.exe TCNTL\xilinxsim.ini TCNTL\xst\dump.xst\TCNTL.prj\ntrc.scr TCNTL\xst\work\hdllib.ref TCNTL\xst\work\hdpdeps.ref TCNTL\xst\work\sub00\vhpl00.vho TCNTL\xst\work\sub00\vhpl01.vho TCNTL\_ngo\netlist.lst TCNTL\_xmsgs\fuse.xmsgs TCNTL\_xmsgs\map.xmsgs TCNTL\_xmsgs\netgen.xmsgs TCNTL\_xmsgs\ngdbuild.xmsgs TCNTL\_xmsgs\par.xmsgs TCNTL\_xmsgs\trce.xmsgs TCNTL\_xmsgs\vhpcomp.xmsgs TCNTL\_xmsgs\xst.xmsgs TCNTL\__ISE_repository_TCNTL.ise_.lock TCNTL\xst\dump.xst\TCNTL.prj\ngx\notopt TCNTL\xst\dump.xst\TCNTL.prj\ngx\opt TCNTL\isim\simprim_ver.auxlib\ffsrce\mingw TCNTL\isim\simprim_ver.auxlib\_x___b_u_f\mingw TCNTL\isim\simprim_ver.auxlib\_x___b_u_f_g_m_u_x\mingw TCNTL\isim\simprim_ver.auxlib\_x___f_f\mingw TCNTL\isim\simprim_ver.auxlib\_x___i_n_v\mingw TCNTL\isim\simprim_ver.auxlib\_x___i_p_a_d\mingw TCNTL\isim\simprim_ver.auxlib\_x___l_u_t4\mingw TCNTL\isim\simprim_ver.auxlib\_x___o_b_u_f\mingw TCNTL\isim\simprim_ver.auxlib\_x___o_n_e\mingw TCNTL\isim\simprim_ver.auxlib\_x___o_p_a_d\mingw TCNTL\isim\simprim_ver.auxlib\_x___z_e_r_o\mingw TCNTL\isim\work\glbl\mingw TCNTL\isim\work\tcntl\mingw TCNTL\isim\work\tcntl_tb\mingw TCNTL\isim\work\_t_c_n_t_l\mingw TCNTL\xst\dump.xst\TCNTL.prj\ngx TCNTL\isim\simprim_ver.auxlib\ffsrce TCNTL\isim\simprim_ver.auxlib\_x___b_u_f TCNTL\isim\simprim_ver.auxlib\_x___b_u_f_g_m_u_x TCNTL\isim\simprim_ver.auxlib\_x___f_f TCNTL\isim\simprim_ver.auxlib\_x___i_n_v TCNTL\isim\simprim_ver.auxlib\_x___i_p_a_d TCNTL\isim\simprim_ver.auxlib\_x___l_u_t4 TCNTL\isim\simprim_ver.auxlib\_x___o_b_u_f TCNTL\isim\simprim_ver.auxlib\_x___o_n_e TCNTL\isim\simprim_ver.auxlib\_x___o_p_a_d TCNTL\isim\simprim_ver.auxlib\_x___z_e_r_o TCNTL\isim\work\glbl TCNTL\isim\work\sub00 TCNTL\isim\work\tcntl TCNTL\isim\work\tcntl_tb TCNTL\isim\work\vlg2D TCNTL\isim\work\vlg59 TCNTL\isim\work\_t_c_n_t_l TCNTL\xst\dump.xst\TCNTL.prj TCNTL\xst\work\sub00 TCNTL\isim\simprim_ver.auxlib TCNTL\isim\work TCNTL\netgen\par TCNTL\netgen\synthesis TCNTL\xst\dump.xst TCNTL\xst\projnav.tmp TCNTL\xst\work TCNTL\isim TCNTL\isim.tmp_save TCNTL\netgen TCNTL\xst TCNTL\_ngo TCNTL\_xmsgs TCNTL